[Bug target/98853] [9/10/11 Regression] wrong use of bfxil at -O1

["cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98853

--- Comment #4 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Jakub Jelinek <jakub@gcc.gnu.org>:

https://gcc.gnu.org/g:55163419211c6f17e3e22c68304384eba35782a3

commit r11-6941-g55163419211c6f17e3e22c68304384eba35782a3
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Wed Jan 27 20:35:21 2021 +0100

    aarch64: Fix up *aarch64_bfxilsi_uxtw [PR98853]

    The https://gcc.gnu.org/legacy-ml/gcc-patches/2018-07/msg01895.html
    patch that introduced this pattern claimed:
    Would generate:

    combine_balanced_int:
            bfxil   w0, w1, 0, 16
            uxtw    x0, w0
            ret

    But with this patch generates:

    combine_balanced_int:
            bfxil   w0, w1, 0, 16
            ret
    and it is indeed what it should generate, but it doesn't do that,
    it emits bfxil  x0, x1, 0, 16
    instead which doesn't zero extend from 32 to 64 bits, but preserves
    the bits from the destination register.

    2021-01-27  Jakub Jelinek  <jakub@redhat.com>

            PR target/98853
            * config/aarch64/aarch64.md (*aarch64_bfxilsi_uxtw): Use
            %w0, %w1 and %2 instead of %0, %1 and %2.

            * gcc.c-torture/execute/pr98853-1.c: New test.
            * gcc.c-torture/execute/pr98853-2.c: New test.