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From: "ubizjak at gmail dot com" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug tree-optimization/98856] [11 Regression] botan AES-128/XTS is
 slower by ~17% since r11-6649-g285fa338b06b804e72997c4d876ecf08a9c083af
Date: Thu, 04 Mar 2021 18:12:09 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D98856

--- Comment #21 from Uro=C5=A1 Bizjak <ubizjak at gmail dot com> ---
(In reply to Uro=C5=A1 Bizjak from comment #20)
> (In reply to Richard Biener from comment #18)
> > Even on Skylake it's 2 (movq) + 3 (vpinsr), so there it's 6 vs. 3.  Not
> > sure if we should somehow do this late somehow (peephole or splitter) s=
ince
> > it requires one more %xmm register.
> What happens if you disparage [v]pinsrd alternatives in vec_concatv2di?

Please try this:

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index db5be59f5b7..edf7b1a3074 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -16043,7 +16043,12 @@
              (const_string "maybe_evex")
           ]
           (const_string "orig")))
-   (set_attr "mode" "TI,TI,TI,TI,TI,TI,V4SF,V2SF,V2SF")])
+   (set_attr "mode" "TI,TI,TI,TI,TI,TI,V4SF,V2SF,V2SF")
+   (set (attr "preferred_for_speed")
+     (cond [(eq_attr "alternative" "0,1,2,3")
+             (symbol_ref "false")
+          ]
+          (symbol_ref "true")))])

 (define_insn "*vec_concatv2di_0"=