From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 3D51A3887011; Fri, 5 Mar 2021 12:52:00 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 3D51A3887011 From: "ubizjak at gmail dot com" To: gcc-bugs@gcc.gnu.org Subject: [Bug tree-optimization/98856] [11 Regression] botan AES-128/XTS is slower by ~17% since r11-6649-g285fa338b06b804e72997c4d876ecf08a9c083af Date: Fri, 05 Mar 2021 12:52:00 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: tree-optimization X-Bugzilla-Version: 11.0 X-Bugzilla-Keywords: missed-optimization, ra X-Bugzilla-Severity: normal X-Bugzilla-Who: ubizjak at gmail dot com X-Bugzilla-Status: ASSIGNED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: rguenth at gcc dot gnu.org X-Bugzilla-Target-Milestone: 11.0 X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-BeenThere: gcc-bugs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-bugs mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 05 Mar 2021 12:52:00 -0000 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D98856 --- Comment #31 from Uro=C5=A1 Bizjak --- (In reply to Richard Biener from comment #29) > The simplified variant below works but IMHO matches cases we do not > want to transform. I can't find any example on how to achieve that > though. I think that pinsrd should be transformed to punpcklqdq irrespective of its first input operand. The insn scheduler should move insns around to mask th= eir latencies. > ;; Further split pinsrq variants of vec_concatv2di with two GPR sources, > ;; one already reloaded, to hide the latency of one GPR->XMM transitions. > (define_peephole2 > [(match_scratch:DI 3 "Yv") > (set (match_operand:V2DI 0 "sse_reg_operand") > (vec_concat:V2DI (match_operand:DI 1 "sse_reg_operand") > (match_operand:DI 2 "nonimmediate_gr_operand")))] > "reload_completed && optimize_insn_for_speed_p ()" Please use "TARGET_64BIT && TARGET_SSE4_1 && !optimize_insn_for_size_p ()" here. > [(set (match_dup 3) > (match_dup 2)) > (set (match_dup 0) > (vec_concat:V2DI (match_dup 1) > (match_dup 3)))])=