From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 240B93950C81; Mon, 8 Mar 2021 15:46:16 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 240B93950C81 From: "amonakov at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug tree-optimization/98856] [11 Regression] botan AES-128/XTS is slower by ~17% since r11-6649-g285fa338b06b804e72997c4d876ecf08a9c083af Date: Mon, 08 Mar 2021 15:46:15 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: tree-optimization X-Bugzilla-Version: 11.0 X-Bugzilla-Keywords: missed-optimization, ra X-Bugzilla-Severity: normal X-Bugzilla-Who: amonakov at gcc dot gnu.org X-Bugzilla-Status: ASSIGNED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: rguenth at gcc dot gnu.org X-Bugzilla-Target-Milestone: 11.0 X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: cc Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-BeenThere: gcc-bugs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-bugs mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 08 Mar 2021 15:46:16 -0000 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D98856 Alexander Monakov changed: What |Removed |Added ---------------------------------------------------------------------------- CC| |amonakov at gcc dot gnu.org --- Comment #38 from Alexander Monakov --- Late to the party, but latency analysis of vpinsrq starting from comment #1= 8 is incorrect: its latency is different with respect to operands. For example, on Zen 2 latency with respect to GPR operand is long (6 cycles, one more that grp->xmm move latency), while latency with respect to XMM ope= rand is just one cycle, same as punpcklqdq. See uops.info, which also shows that vpinsrq involves 2 uops, and it's easy to guess what they are: first uop is= for gpr->xmm inter-unit move (latency 5), and the second is SSE merge: https://uops.info/html-instr/VPINSRQ_XMM_XMM_R64_I8.html https://uops.info/html-instr/VMOVD_XMM_R32.html So in the CPU backend there's not much difference between movq pinsrq and movq movq punpcklqdq both have same uops and overall latency (1 + movq latency). (though on Intel starting from Haswell pinsrq oddly has latency 2 w.r.t xmm operand, but on Ice Lake it is again 1 cycle).=