From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 80C0A3861039; Fri, 5 Feb 2021 17:55:52 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 80C0A3861039 From: "jakub at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug tree-optimization/98856] [11 Regression] botan AES-128/XTS is slower by ~17% since r11-6649-g285fa338b06b804e72997c4d876ecf08a9c083af Date: Fri, 05 Feb 2021 17:55:52 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: tree-optimization X-Bugzilla-Version: 11.0 X-Bugzilla-Keywords: missed-optimization X-Bugzilla-Severity: normal X-Bugzilla-Who: jakub at gcc dot gnu.org X-Bugzilla-Status: ASSIGNED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: rguenth at gcc dot gnu.org X-Bugzilla-Target-Milestone: 11.0 X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-BeenThere: gcc-bugs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-bugs mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 05 Feb 2021 17:55:52 -0000 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D98856 --- Comment #14 from Jakub Jelinek --- WIP that implements that. Except that we need some permutation expansion improvements, both for the SSE2 V4SImode permutation cases and for AVX2 V8SImode permutation cases. --- gcc/config/i386/sse.md.jj 2021-02-05 14:32:44.175463716 +0100 +++ gcc/config/i386/sse.md 2021-02-05 18:49:29.621590903 +0100 @@ -12458,7 +12458,7 @@ (set_attr "prefix" "orig,vex") (set_attr "mode" "")]) -(define_insn "ashr3" +(define_insn "ashr3" [(set (match_operand:VI248_AVX512BW_AVX512VL 0 "register_operand" "=3Dv,= v") (ashiftrt:VI248_AVX512BW_AVX512VL (match_operand:VI248_AVX512BW_AVX512VL 1 "nonimmediate_operand" "v,vm") @@ -12472,6 +12472,125 @@ (const_string "0"))) (set_attr "mode" "")]) +(define_expand "ashr3" + [(set (match_operand:VI248_AVX512BW 0 "register_operand") + (ashiftrt:VI248_AVX512BW + (match_operand:VI248_AVX512BW 1 "nonimmediate_operand") + (match_operand:DI 2 "nonmemory_operand")))] + "TARGET_AVX512F") + +(define_expand "ashrv4di3" + [(set (match_operand:V4DI 0 "register_operand") + (ashiftrt:V4DI + (match_operand:V4DI 1 "nonimmediate_operand") + (match_operand:DI 2 "nonmemory_operand")))] + "TARGET_AVX2" +{ + if (!TARGET_AVX512VL) + { + if (CONST_INT_P (operands[2]) && UINTVAL (operands[2]) >=3D 63) + { + rtx zero =3D force_reg (V4DImode, CONST0_RTX (V4DImode)); + emit_insn (gen_avx2_gtv4di3 (operands[0], zero, operands[1])); + DONE; + } + if (operands[2] =3D=3D const0_rtx) + { + emit_move_insn (operands[0], operands[1]); + DONE; + } + if (CONST_INT_P (operands[2])) + { + vec_perm_builder sel (8, 8, 1); + sel.quick_grow (8); + rtx arg0, arg1; + rtx op1 =3D lowpart_subreg (V8SImode, operands[1], V4DImode); + rtx target =3D gen_reg_rtx (V8SImode); + if (INTVAL (operands[2]) > 32) + { + arg0 =3D gen_reg_rtx (V8SImode); + arg1 =3D gen_reg_rtx (V8SImode); + emit_insn (gen_ashrv8si3 (arg1, op1, GEN_INT (31))); + emit_insn (gen_ashrv8si3 (arg0, op1, + GEN_INT (INTVAL (operands[2]) - 32)= )); + sel[0] =3D 1; + sel[1] =3D 9; + sel[2] =3D 3; + sel[3] =3D 11; + sel[4] =3D 5; + sel[5] =3D 13; + sel[6] =3D 7; + sel[7] =3D 15; + } + else if (INTVAL (operands[2]) =3D=3D 32) + { + arg0 =3D op1; + arg1 =3D gen_reg_rtx (V8SImode); + emit_insn (gen_ashrv8si3 (arg1, op1, GEN_INT (31))); + sel[0] =3D 1; + sel[1] =3D 9; + sel[2] =3D 3; + sel[3] =3D 11; + sel[4] =3D 5; + sel[5] =3D 13; + sel[6] =3D 7; + sel[7] =3D 15; + } + else + { + arg0 =3D gen_reg_rtx (V2DImode); + arg1 =3D gen_reg_rtx (V4SImode); + emit_insn (gen_lshrv2di3 (arg0, operands[1], operands[2])); + emit_insn (gen_ashrv4si3 (arg1, op1, operands[2])); + arg0 =3D lowpart_subreg (V4SImode, arg0, V2DImode); + sel[0] =3D 0; + sel[1] =3D 9; + sel[2] =3D 2; + sel[3] =3D 11; + sel[4] =3D 4; + sel[5] =3D 13; + sel[6] =3D 6; + sel[7] =3D 15; + } + vec_perm_indices indices (sel, 2, 8); + bool ok =3D targetm.vectorize.vec_perm_const (V8SImode, target, + arg0, arg1, indices); + gcc_assert (ok); + emit_move_insn (operands[0], + lowpart_subreg (V4DImode, target, V8SImode)); + DONE; + } + + rtx zero =3D force_reg (V4DImode, CONST0_RTX (V4DImode)); + rtx zero_or_all_ones =3D gen_reg_rtx (V4DImode); + emit_insn (gen_avx2_gtv4di3 (zero_or_all_ones, zero, operands[1])); + rtx lshr_res =3D gen_reg_rtx (V4DImode); + emit_insn (gen_lshrv4di3 (lshr_res, operands[1], operands[2])); + rtx ashl_res =3D gen_reg_rtx (V4DImode); + rtx amount; + if (TARGET_64BIT) + { + amount =3D gen_reg_rtx (DImode); + emit_insn (gen_subdi3 (amount, force_reg (DImode, GEN_INT (64)), + operands[2])); + } + else + { + rtx temp =3D gen_reg_rtx (SImode); + emit_insn (gen_subsi3 (temp, force_reg (SImode, GEN_INT (64)), + lowpart_subreg (SImode, operands[2], + DImode))); + amount =3D gen_reg_rtx (V4SImode); + emit_insn (gen_vec_setv4si_0 (amount, CONST0_RTX (V4SImode), + temp)); + } + amount =3D lowpart_subreg (DImode, amount, GET_MODE (amount)); + emit_insn (gen_ashlv4di3 (ashl_res, zero_or_all_ones, amount)); + emit_insn (gen_iorv4di3 (operands[0], lshr_res, ashl_res)); + DONE; + } +}) + (define_insn "3" [(set (match_operand:VI248_AVX512BW_2 0 "register_operand" "=3Dv,v") (any_lshift:VI248_AVX512BW_2 @@ -20313,11 +20432,13 @@ (ashiftrt:V2DI (match_operand:V2DI 1 "register_operand") (match_operand:DI 2 "nonmemory_operand")))] - "TARGET_SSE4_2" + "TARGET_SSE2" { if (!TARGET_AVX512VL) { - if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) =3D=3D 63) + if (TARGET_SSE4_2 + && CONST_INT_P (operands[2]) + && UINTVAL (operands[2]) >=3D 63) { rtx zero =3D force_reg (V2DImode, CONST0_RTX (V2DImode)); emit_insn (gen_sse4_2_gtv2di3 (operands[0], zero, operands[1])); @@ -20328,6 +20449,65 @@ emit_move_insn (operands[0], operands[1]); DONE; } + if (CONST_INT_P (operands[2]) + && (!TARGET_XOP || UINTVAL (operands[2]) >=3D 63)) + { + vec_perm_builder sel (4, 4, 1); + sel.quick_grow (4); + rtx arg0, arg1; + rtx op1 =3D lowpart_subreg (V4SImode, operands[1], V2DImode); + rtx target =3D gen_reg_rtx (V4SImode); + if (UINTVAL (operands[2]) >=3D 63) + { + arg0 =3D arg1 =3D gen_reg_rtx (V4SImode); + emit_insn (gen_ashrv4si3 (arg0, op1, GEN_INT (31))); + sel[0] =3D 1; + sel[1] =3D 1; + sel[2] =3D 3; + sel[3] =3D 3; + } + else if (INTVAL (operands[2]) > 32) + { + arg0 =3D gen_reg_rtx (V4SImode); + arg1 =3D gen_reg_rtx (V4SImode); + emit_insn (gen_ashrv4si3 (arg1, op1, GEN_INT (31))); + emit_insn (gen_ashrv4si3 (arg0, op1, + GEN_INT (INTVAL (operands[2]) - 32)= )); + sel[0] =3D 1; + sel[1] =3D 5; + sel[2] =3D 3; + sel[3] =3D 7; + } + else if (INTVAL (operands[2]) =3D=3D 32) + { + arg0 =3D op1; + arg1 =3D gen_reg_rtx (V4SImode); + emit_insn (gen_ashrv4si3 (arg1, op1, GEN_INT (31))); + sel[0] =3D 1; + sel[1] =3D 5; + sel[2] =3D 3; + sel[3] =3D 7; + } + else + { + arg0 =3D gen_reg_rtx (V2DImode); + arg1 =3D gen_reg_rtx (V4SImode); + emit_insn (gen_lshrv2di3 (arg0, operands[1], operands[2])); + emit_insn (gen_ashrv4si3 (arg1, op1, operands[2])); + arg0 =3D lowpart_subreg (V4SImode, arg0, V2DImode); + sel[0] =3D 0; + sel[1] =3D 5; + sel[2] =3D 2; + sel[3] =3D 7; + } + vec_perm_indices indices (sel, arg0 !=3D arg1 ? 2 : 1, 4); + bool ok =3D targetm.vectorize.vec_perm_const (V4SImode, target, + arg0, arg1, indices); + gcc_assert (ok); + emit_move_insn (operands[0], + lowpart_subreg (V2DImode, target, V4SImode)); + DONE; + } if (!TARGET_XOP) { rtx zero =3D force_reg (V2DImode, CONST0_RTX (V2DImode)); @@ -20337,9 +20517,7 @@ emit_insn (gen_lshrv2di3 (lshr_res, operands[1], operands[2])); rtx ashl_res =3D gen_reg_rtx (V2DImode); rtx amount; - if (CONST_INT_P (operands[2])) - amount =3D GEN_INT (64 - INTVAL (operands[2])); - else if (TARGET_64BIT) + if (TARGET_64BIT) { amount =3D gen_reg_rtx (DImode); emit_insn (gen_subdi3 (amount, force_reg (DImode, GEN_INT (64= )), @@ -20355,8 +20533,7 @@ emit_insn (gen_vec_setv4si_0 (amount, CONST0_RTX (V4SImode), temp)); } - if (!CONST_INT_P (operands[2])) - amount =3D lowpart_subreg (DImode, amount, GET_MODE (amount)); + amount =3D lowpart_subreg (DImode, amount, GET_MODE (amount)); emit_insn (gen_ashlv2di3 (ashl_res, zero_or_all_ones, amount)); emit_insn (gen_iorv2di3 (operands[0], lshr_res, ashl_res)); DONE;=