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From: "pinskia at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug target/98867] Failure to use SRI instruction for
 shift-right-and-insert vector operations
Date: Thu, 04 Feb 2021 07:10:07 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D98867

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Last reconfirmed|                            |2021-02-04
           Severity|normal                      |enhancement
     Ever confirmed|0                           |1
             Status|UNCONFIRMED                 |NEW

--- Comment #1 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
>This may be a bit too complex for combine to match though
I don't think so really:

Trying 18, 13 -> 19:
   18: r110:V16QI=3Dr111:V16QI&r112:V16QI
      REG_DEAD r111:V16QI
      REG_EQUAL r111:V16QI&const_vector
   13: r106:V16QI=3Dr107:V16QI 0>>const_vector
      REG_DEAD r107:V16QI
   19: r113:V16QI=3Dr106:V16QI|r110:V16QI
      REG_DEAD r110:V16QI
      REG_DEAD r106:V16QI
Failed to match this instruction:
(set (reg:V16QI 113 [ vect__6.15 ])
    (ior:V16QI (and:V16QI (reg:V16QI 111 [ MEM[symbol: out, index: ivtmp.22=
_30,
offset: 0B] ])
            (reg:V16QI 112))
        (lshiftrt:V16QI (reg:V16QI 107 [ MEM[symbol: in, index: ivtmp.22_30,
offset: 0B] ])
            (const_vector:V16QI [
                    (const_int 6 [0x6]) repeated x16
                ]))))


The only problem is (reg:V16QI 112) was not replaced with const_vector, tha=
t it
was formed from.
But insn 18 does have this REG_EQUAL:
        (expr_list:REG_EQUAL (and:V16QI (reg:V16QI 111 [ MEM[symbol: out,
index: ivtmp.22_30, offset: 0B] ])
                (const_vector:V16QI [
                        (const_int -4 [0xfffffffffffffffc]) repeated x16
                    ]))

So it might be easy to match, just combine is not showing all of what is be=
ing
tried?
So maybe adding a pattern for it might be easy ....=