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From: "bergner at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug target/99041] combine creates invalid address which ICEs in
 decompose_normal_address
Date: Wed, 10 Feb 2021 20:51:10 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D99041

Peter Bergner <bergner at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|NEW                         |ASSIGNED

--- Comment #6 from Peter Bergner <bergner at gcc dot gnu.org> ---
(In reply to Peter Bergner from comment #3)
> Ahh, ok.  I can make that more robust.  Thanks for the pointer!

The mma_assemble_pair/mma_assemble_acc patterns both generate lxv or lxvp
instructions, which both use a DQ offset and we already have function to te=
st
for that.  The following change fixes the ICE, so I'll give it a spin on
regtesting.

diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates=
.md
index 76328ecff3d..bd26c62b3a4 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -1156,7 +1156,9 @@
 ;; Return 1 if this operand is valid for a MMA assemble accumulator insn.
 (define_special_predicate "mma_assemble_input_operand"
   (match_test "(mode =3D=3D V16QImode
-               && (vsx_register_operand (op, mode) || MEM_P (op)))"))
+               && (vsx_register_operand (op, mode)
+                   || (MEM_P (op)
+                       && quad_address_p (XEXP (op, 0), mode, false))))"))

 ;; Return 1 if this operand is valid for an MMA disassemble insn.
 (define_predicate "mma_disassemble_output_operand"=