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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/99195] Optimise away vec_concat of 64-bit AdvancedSIMD
 operations with zeroes in aarch64
Date: Thu, 25 May 2023 14:01:15 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D99195

--- Comment #17 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Kyrylo Tkachov <ktkachov@gcc.gnu.org>:

https://gcc.gnu.org/g:560bb845321f5ad039a318a081b0e88d9900f5cb

commit r14-1241-g560bb845321f5ad039a318a081b0e88d9900f5cb
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Thu May 25 15:00:16 2023 +0100

    aarch64: PR target/99195 Annotate complex FP patterns for vec-concat-ze=
ro

    This patch annotates the complex add and mla patterns for vec-concat-ze=
ro.
    Testing showed an interesting bug in our MD patterns where they were
defined to match:
            (plus:VHSDF (match_operand:VHSDF 1 "register_operand" "0")
                        (unspec:VHSDF [(match_operand:VHSDF 2
"register_operand" "w")
                                       (match_operand:VHSDF 3
"register_operand" "w")
                                       (match_operand:SI 4 "const_int_opera=
nd"
"n")]
                                       FCMLA))

    but the canonicalisation rules for PLUS require the more "complex" oper=
and
to be first so
    during combine when the new substituted patterns were attempted to be
formed combine/recog would
    try to match:
    (plus:V2SF (unspec:V2SF [
                            (reg:V2SF 100)
                            (reg:V2SF 101)
                            (const_int 0 [0])
                        ] UNSPEC_FCMLA270)
                    (reg:V2SF 99))
    instead. This patch fixes the operands of the PLUS RTX in these pattern=
s.
    Similar patterns for the dot-product instructions already used the right
order.

    Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-e=
lf.

    gcc/ChangeLog:

            PR target/99195
            * config/aarch64/aarch64-simd.md (aarch64_fcadd<rot><mode>): Re=
name
to...
            (aarch64_fcadd<rot><mode><vczle><vczbe>): ... This.
            Fix canonicalization of PLUS operands.
            (aarch64_fcmla<rot><mode>): Rename to...
            (aarch64_fcmla<rot><mode><vczle><vczbe>): ... This.
            Fix canonicalization of PLUS operands.
            (aarch64_fcmla_lane<rot><mode>): Rename to...
            (aarch64_fcmla_lane<rot><mode><vczle><vczbe>): ... This.
            Fix canonicalization of PLUS operands.
            (aarch64_fcmla_laneq<rot>v4hf): Rename to...
            (aarch64_fcmla_laneq<rot>v4hf<vczle><vczbe>): ... This.
            Fix canonicalization of PLUS operands.
            (aarch64_fcmlaq_lane<rot><mode>): Fix canonicalization of PLUS
operands.

    gcc/testsuite/ChangeLog:

            PR target/99195
            * gcc.target/aarch64/simd/pr99195_9.c: New test.=