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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug target/99195] Optimise away vec_concat of 64-bit AdvancedSIMD
 operations with zeroes in aarch64
Date: Fri, 28 Apr 2023 08:34:27 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D99195

--- Comment #6 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Kyrylo Tkachov <ktkachov@gcc.gnu.org>:

https://gcc.gnu.org/g:889a0791c632aa2804c4e01cc7dddca1ae0d229c

commit r14-320-g889a0791c632aa2804c4e01cc7dddca1ae0d229c
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Fri Apr 28 09:33:16 2023 +0100

    aarch64: PR target/99195 annotate more integer unary patterns for
vec-concat with zero

    More of the straightforward cases to annotate plus tests, this time for
simple integer unary ops.
    Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-e=
lf.

    gcc/ChangeLog:

            PR target/99195
            * config/aarch64/aarch64-simd.md (aarch64_rbit<mode>): Rename t=
o...
            (aarch64_rbit<mode><vczle><vczbe>): ... This.
            (neg<mode>2): Rename to...
            (neg<mode>2<vczle><vczbe>): ... This.
            (abs<mode>2): Rename to...
            (abs<mode>2<vczle><vczbe>): ... This.
            (aarch64_abs<mode>): Rename to...
            (aarch64_abs<mode><vczle><vczbe>): ... This.
            (one_cmpl<mode>2): Rename to...
            (one_cmpl<mode>2<vczle><vczbe>): ... This.
            (clrsb<mode>2): Rename to...
            (clrsb<mode>2<vczle><vczbe>): ... This.
            (clz<mode>2): Rename to...
            (clz<mode>2<vczle><vczbe>): ... This.
            (popcount<mode>2): Rename to...
            (popcount<mode>2<vczle><vczbe>): ... This.

    gcc/testsuite/ChangeLog:

            PR target/99195
            * gcc.target/aarch64/simd/pr99195_1.c: Add tests for unary inte=
ger
ops.=