From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 29EB1393BC04; Mon, 1 Mar 2021 17:45:07 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 29EB1393BC04 From: "cvs-commit at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/99271] [10 regression] Wrong code for Arm-v8-m.main CMSE calling __gnu_cmse_nonsecure_call Date: Mon, 01 Mar 2021 17:45:07 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 10.0 X-Bugzilla-Keywords: wrong-code X-Bugzilla-Severity: normal X-Bugzilla-Who: cvs-commit at gcc dot gnu.org X-Bugzilla-Status: ASSIGNED X-Bugzilla-Resolution: X-Bugzilla-Priority: P1 X-Bugzilla-Assigned-To: rearnsha at gcc dot gnu.org X-Bugzilla-Target-Milestone: 10.3 X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-BeenThere: gcc-bugs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-bugs mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 01 Mar 2021 17:45:07 -0000 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D99271 --- Comment #3 from CVS Commits --- The releases/gcc-10 branch has been updated by Richard Earnshaw : https://gcc.gnu.org/g:1b3bb23a576e6a864f540e3bea5097f47fea507c commit r10-9398-g1b3bb23a576e6a864f540e3bea5097f47fea507c Author: Richard Earnshaw Date: Mon Feb 22 15:00:53 2021 +0000 arm: force use of r4 for __gnu_cmse_nonsecure_call when !FPCXT [PR99271] Commit r10-6017 relaxed the constraint on thumb2 calls to __gnu_cmse_nonsecure_call to allow any register for the call address. Although the initial code expansion continues to use r4 with the FPCXT extension is not enabled, the change was unsafe because subsequent optimizations could use the additional freedom to change which register was being used. To fix this we need to split the output patterns in the machine description to use distinct recognizers: one with the additional freedom when FPCXT is enabled an another that retains the original restrictions when the extension is not available. gcc: PR target/99271 * config/arm/thumb2.md (nonsecure_call_reg_thumb2_fpcxt): New pattern. (nonsecure_call_value_reg_thumb2_fpcxt): Likewise. (nonsecure_call_reg_thumb2): Restrict to using r4 for the callee address and disable when the FPCXT is not available. (nonsecure_call_value_reg_thumb2): Likewise. gcc/testsuite: * gcc.target/arm/cmse/cmse-18.c: New test.=