From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 74F69385843D; Thu, 12 Jan 2023 13:42:30 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 74F69385843D DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1673530950; bh=FZmLG1qd/opMSzPRIt7Vr6H9s/gK6kaNxJwSbKUlNqk=; h=From:To:Subject:Date:In-Reply-To:References:From; b=Fa3xpiz2dAevWRTZJpyLoM2ObClFaWAsMqHcqFcGCgOGzOooZoHFMIGEhfMY+QXQx wpbr3W9ddjL4EOryOyoHh6+PSr+7xURuraqhhjQGJe/vZcYddkzu4C64A0YRdH7Nbj XxohWpFaXTVfJCS/H7sOFmV3Mve/Fue/+J2rHjwc= From: "rguenth at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug tree-optimization/99412] s352 benchmark of TSVC is vectorized by clang and not by gcc Date: Thu, 12 Jan 2023 13:42:30 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: tree-optimization X-Bugzilla-Version: 11.0 X-Bugzilla-Keywords: missed-optimization X-Bugzilla-Severity: normal X-Bugzilla-Who: rguenth at gcc dot gnu.org X-Bugzilla-Status: RESOLVED X-Bugzilla-Resolution: FIXED X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: rguenth at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: bug_status resolution Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D99412 Richard Biener changed: What |Removed |Added ---------------------------------------------------------------------------- Status|ASSIGNED |RESOLVED Resolution|--- |FIXED --- Comment #6 from Richard Biener --- GCC now does .L2: vmovaps b(%rax), %xmm6 vmulps a(%rax), %xmm6, %xmm0 addq $80, %rax vmovaps b-64(%rax), %xmm7 vmovaps b-48(%rax), %xmm6 vaddps %xmm0, %xmm5, %xmm5 vmulps a-64(%rax), %xmm7, %xmm0 vmovaps b-32(%rax), %xmm7 vaddps %xmm0, %xmm1, %xmm1 vmulps a-48(%rax), %xmm6, %xmm0 vmovaps b-16(%rax), %xmm6 vaddps %xmm0, %xmm4, %xmm4 vmulps a-32(%rax), %xmm7, %xmm0 vaddps %xmm0, %xmm2, %xmm2 vmulps a-16(%rax), %xmm6, %xmm0 vaddps %xmm0, %xmm3, %xmm3 cmpq $128000, %rax jne .L2 thus uses a VF of 4 with -Ofast. Your LLVM snippet uses 5 lanes instead of our 20 with four lanes in a V4SF and one lane in a scalar. That's interesting but not something we support. Re-rolling would mean using a single v4sf 4 lane vector here. For a pure SLP loop something like this should be possible without too much hassle I think. We'd just need to try ... (and think of if it's worth in real life) For the purpose of the Summary this is fixed now.=