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Subject: [Bug target/99437] [11 Regression] Error: immediate value out of
 range 1 to 8 at operand 3 -- `shrn v1.8b,v1.8h,15'
Date: Mon, 08 Mar 2021 15:06:21 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D99437

--- Comment #5 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Kyrylo Tkachov <ktkachov@gcc.gnu.org>:

https://gcc.gnu.org/g:0d9a70ea3881c284b7689b691d54d047b55b486d

commit r11-7556-g0d9a70ea3881c284b7689b691d54d047b55b486d
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Mon Mar 8 15:05:21 2021 +0000

    aarch64: Fix PR99437 - tighten shift predicates for narrowing shift
patterns

    In this bug combine forms the (R)SHRN(2) instructions with an invalid s=
hift
amount.
    The intrinsic expanders for these patterns validate the right shift amo=
unt
but if the
    final patterns end up being matched by combine (or other RTL passes I
suppose) they
    still let the wrong const_vector through.

    This patch tightens up the predicates for the instructions involved by
using predicates
    for the right shift amount const_vectors.

    gcc/ChangeLog:

            PR target/99437
            * config/aarch64/predicates.md (aarch64_simd_shift_imm_vec_qi):
Define.
            (aarch64_simd_shift_imm_vec_hi): Likewise.
            (aarch64_simd_shift_imm_vec_si): Likewise.
            (aarch64_simd_shift_imm_vec_di): Likewise.
            * config/aarch64/aarch64-simd.md (aarch64_shrn<mode>_insn_le): =
Use
            predicate from above.
            (aarch64_shrn<mode>_insn_be): Likewise.
            (aarch64_rshrn<mode>_insn_le): Likewise.
            (aarch64_rshrn<mode>_insn_be): Likewise.
            (aarch64_shrn2<mode>_insn_le): Likewise.
            (aarch64_shrn2<mode>_insn_be): Likewise.
            (aarch64_rshrn2<mode>_insn_le): Likewise.
            (aarch64_rshrn2<mode>_insn_be): Likewise.

    gcc/testsuite/ChangeLog:

            PR target/99437
            * gcc.target/aarch64/simd/pr99437.c: New test.=