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From: "marxin at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug target/99702] [11 Regression] ICE: RTL check: expected code
 'const_int', have 'subreg' in riscv_expand_block_move, at
 config/riscv/riscv.c:3262 with memcpy() since
 r11-7757-gfc9c4e5fc50c7fcbd27d6cb3dd372f7da8216954
Date: Mon, 22 Mar 2021 08:26:06 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D99702

Martin Li=C5=A1ka <marxin at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
            Summary|[11 Regression] ICE: RTL    |[11 Regression] ICE: RTL
                   |check: expected code        |check: expected code
                   |'const_int', have 'subreg'  |'const_int', have 'subreg'
                   |in riscv_expand_block_move, |in riscv_expand_block_move,
                   |at                          |at
                   |config/riscv/riscv.c:3262   |config/riscv/riscv.c:3262
                   |with memcpy()               |with memcpy() since
                   |                            |r11-7757-gfc9c4e5fc50c7fcbd
                   |                            |27d6cb3dd372f7da8216954
             Status|UNCONFIRMED                 |NEW
     Ever confirmed|0                           |1
   Last reconfirmed|                            |2021-03-22
   Target Milestone|---                         |11.0
                 CC|                            |marxin at gcc dot gnu.org,
                   |                            |sinan.lin at aalto dot fi
      Known to work|                            |10.2.0

--- Comment #2 from Martin Li=C5=A1ka <marxin at gcc dot gnu.org> ---
Started with r11-7757-gfc9c4e5fc50c7fcbd27d6cb3dd372f7da8216954.=