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From: "jakub at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug target/99718] [11 regression] ICE in new test case
 gcc.target/powerpc/pr98914.c  for 32 bits
Date: Tue, 23 Mar 2021 12:44:55 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D99718

Jakub Jelinek <jakub at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |jakub at gcc dot gnu.org

--- Comment #3 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
(In reply to luoxhu from comment #1)
> Confirmed.  Another case forgot to test m32 again :(
>=20
> David mentioned no need variable vec_insert support for m32 build, so I
> think we should avoid generating IFN VEC_SET in
> gimple-isel.c:gimple_expand_vec_set_expr, but it seems not possible to ch=
eck
> "TARGET_P8_VECTOR && TARGET_DIRECT_MOVE_64BIT" in the common file or thro=
ugh
> can_vec_set_var_idx_p. Any suggestions?
>=20
> https://gcc.gnu.org/pipermail/gcc-patches/2021-January/564403.html

If the non-constant vec_set can't be supported when
!(TARGET_P8_VECTOR && TARGET_DIRECT_MOVE_64BIT)
then
(define_expand "vec_set<mode>"
  [(match_operand:VEC_E 0 "vlogical_operand")
   (match_operand:<VEC_base> 1 "register_operand")
   (match_operand 2 "reg_or_cint_operand")]
  "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
  rs6000_expand_vector_set (operands[0], operands[1], operands[2]);
  DONE;
})
should be changed, perhaps add a new predicate that for
TARGET_P8_VECTOR && TARGET_DIRECT_MOVE_64BIT
is equivalent to reg_or_cint_operand and otherwise to const_int_operand?
(define_predicate "vec_set_index_operand"
  (if_then_else (match_test "TARGET_P8_VECTOR && TARGET_DIRECT_MOVE_64BIT")
    (match_operand 0 "reg_or_cint_operand")
    (match_operand 0 "const_int_operand")))=