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From: "jakub at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/99724] [11 Regression] CE in in extract_insn, at
 recog.c:2770
Date: Tue, 23 Mar 2021 13:37:25 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D99724

--- Comment #3 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
E.g. I can't find a neg pattern in iwmmxt.md either, so
r11-5990-g4cbb7cab47a3b91a12ad52baab5bbe6e4373ce73
is problematic too.
And r11-6616-g25bef68902f42f414f99626cefb2d3df81de7dc8 too (don't see any
UNSPEC_MISALIGNED_ACCESS in iwmmxt.md either.
and/ior/xor is, so that is likely ok.
So
--- gcc/config/arm/vec-common.md.jj     2021-03-23 10:21:07.096448805 +0100
+++ gcc/config/arm/vec-common.md        2021-03-23 14:36:54.823323029 +0100
@@ -202,13 +202,13 @@ (define_expand "xor<mode>3"
 (define_expand "one_cmpl<mode>2"
   [(set (match_operand:VDQ 0 "s_register_operand")
        (not:VDQ (match_operand:VDQ 1 "s_register_operand")))]
-  "ARM_HAVE_<MODE>_ARITH"
+  "ARM_HAVE_<MODE>_ARITH && !TARGET_REALLY_IWMMXT"
 )

 (define_expand "neg<mode>2"
   [(set (match_operand:VDQWH 0 "s_register_operand" "")
        (neg:VDQWH (match_operand:VDQWH 1 "s_register_operand" "")))]
-  "ARM_HAVE_<MODE>_ARITH"
+  "ARM_HAVE_<MODE>_ARITH && !TARGER_REALLY_IWMMXT"
 )

 (define_expand "cadd<rot><mode>3"
@@ -281,7 +281,8 @@ (define_expand "movmisalign<mode>"
  [(set (match_operand:VDQX 0 "neon_perm_struct_or_reg_operand")
        (unspec:VDQX [(match_operand:VDQX 1 "neon_perm_struct_or_reg_operan=
d")]
         UNSPEC_MISALIGNED_ACCESS))]
- "ARM_HAVE_<MODE>_LDST && !BYTES_BIG_ENDIAN && unaligned_access"
+ "ARM_HAVE_<MODE>_LDST && !BYTES_BIG_ENDIAN
+  && unaligned_access && !TARGET_REALLY_IWMMXT"
 {
  rtx adjust_mem;
  /* This pattern is not permitted to fail during expansion: if both argume=
nts
instead?=