From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id B06673861021; Tue, 23 Mar 2021 21:55:38 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org B06673861021 From: "clyon at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/99727] [11 Regression] MVE: ICE (segfault) in arm_print_operand at -O3 since r11-6616-g25bef689 Date: Tue, 23 Mar 2021 21:55:38 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 11.0 X-Bugzilla-Keywords: ice-on-valid-code X-Bugzilla-Severity: normal X-Bugzilla-Who: clyon at gcc dot gnu.org X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: 11.0 X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: bug_status cf_reconfirmed_on everconfirmed Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-BeenThere: gcc-bugs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-bugs mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 23 Mar 2021 21:55:38 -0000 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D99727 Christophe Lyon changed: What |Removed |Added ---------------------------------------------------------------------------- Status|UNCONFIRMED |NEW Last reconfirmed| |2021-03-23 Ever confirmed|0 |1 --- Comment #2 from Christophe Lyon --- Looks like a constraint problem: I kept the Um constraint as used by Neon, while MVE needs Ux. This patch fixes the ICE: diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 440fd6a..1351863 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -10858,7 +10858,7 @@ (define_insn "arm_vcx3q_p_v16qi" ) (define_insn "*movmisalign_mve_store" - [(set (match_operand:MVE_VLD_ST 0 "neon_permissive_struct_operand"=20=20= =20=20=20=20=20 "=3DUm") + [(set (match_operand:MVE_VLD_ST 0 "neon_permissive_struct_operand"=20=20= =20=20=20=20=20 "=3DUx") (unspec:MVE_VLD_ST [(match_operand:MVE_VLD_ST 1 "s_register_operand= " " w")] UNSPEC_MISALIGNED_ACCESS))] "((TARGET_HAVE_MVE && VALID_MVE_SI_MODE (mode)) @@ -10871,7 +10871,7 @@ (define_insn "*movmisalign_mve_store" (define_insn "*movmisalign_mve_load" [(set (match_operand:MVE_VLD_ST 0 "s_register_operand"=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 "=3Dw") - (unspec:MVE_VLD_ST [(match_operand:MVE_VLD_ST 1 "neon_permissive_struct_operand" " Um")] + (unspec:MVE_VLD_ST [(match_operand:MVE_VLD_ST 1 "neon_permissive_struct_operand" " Ux")] UNSPEC_MISALIGNED_ACCESS))] "((TARGET_HAVE_MVE && VALID_MVE_SI_MODE (mode)) || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (mode)))=