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From: "acoplan at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug target/99766] [11 Regression] ICE: unable to generate reloads
 with SVE code since r11-7807-gbe70bb5e
Date: Fri, 26 Mar 2021 11:57:23 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D99766

--- Comment #7 from Alex Coplan <acoplan at gcc dot gnu.org> ---
Here is a testcase with SVE intrinsics that ICEs in the same way at -Os:

$ cat test.cc
#include <arm_sve.h>
char a;
void c(unsigned &, const unsigned &);
void d(char, bool, short, int, int, char e, int, short f, unsigned g) {
  for (int h; h; h++)
    c(g, f);
  while (e)
    a =3D svaddv(svptrue_pat_b8(SV_VL1),
        svadd_z(svptrue_b8 (), svdup_s8(g), 0));
}
$ aarch64-linux-gnu-gcc -c -Os test.cc -march=3Darmv8.2-a+sve
test.cc: In function =E2=80=98void d(char, bool, short int, int, int, char,=
 int, short
int, unsigned int)=E2=80=99:
test.cc:10:1: error: unable to generate reloads for:
   10 | }
      | ^
(insn 39 89 40 5 (set (reg:VNx16QI 121 [ _5 ])
        (unspec:VNx16QI [
                (reg:VNx16BI 119)
                (vec_duplicate:VNx16QI (mem/c:QI (plus:DI (reg/f:DI 65 ap)
                            (const_int 64 [0x40])) [1 g+0 S1 A128]))
                (const_vector:VNx16QI [
                        (const_int 0 [0])
                    ])
            ] UNSPEC_SEL)) "test.cc":8:15 4782 {sve_ld1rvnx16qi}
     (expr_list:REG_DEAD (reg:VNx16BI 119)
        (nil)))
during RTL pass: reload
test.cc:10:1: internal compiler error: in curr_insn_transform, at
lra-constraints.c:4133=