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From: "jakub at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug c/99810] Wrong const evaluation of 64-bit division
Date: Mon, 29 Mar 2021 08:14:50 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D99810

Jakub Jelinek <jakub at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |RESOLVED
         Resolution|---                         |INVALID

--- Comment #4 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
.word in ARM assembly is 32-bit, so it is not wrong.
64-bit values need to be put into two hw registers, and there is not a sing=
le
instruction to put 0x886b6600 into a 32-bit register, but there is a single
instruction to put 0xfffffff1 into a 32-bit register, so the code loads one
part from the constant pool and the other part uses mvn instruction (move
negated) with a small immediate.=