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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/99842] MMA test case ICEs using -O3
Date: Mon, 31 May 2021 03:46:42 +0000 [thread overview]
Message-ID: <bug-99842-4-UeAJzXNDdj@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-99842-4@http.gcc.gnu.org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99842
--- Comment #4 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Peter Bergner <bergner@gcc.gnu.org>:
https://gcc.gnu.org/g:df4e0359dad239854af0ea9eacb8e7e3719557d0
commit r12-1127-gdf4e0359dad239854af0ea9eacb8e7e3719557d0
Author: Peter Bergner <bergner@linux.ibm.com>
Date: Sun May 30 22:45:55 2021 -0500
rs6000: MMA test case ICEs using -O3 [PR99842]
The mma_assemble_input_operand predicate does not accept reg+reg indexed
addresses which can lead to ICEs. The lxv and lxvp instructions have
indexed forms (lxvx and lxvpx), so the simple solution is to just allow
indexed addresses in the predicate.
2021-05-30 Peter Bergner <bergner@linux.ibm.com>
gcc/
PR target/99842
* config/rs6000/predicates.md(mma_assemble_input_operand): Allow
indexed form addresses.
gcc/testsuite/
PR target/99842
* g++.target/powerpc/pr99842.C: New.
next prev parent reply other threads:[~2021-05-31 3:46 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-30 23:12 [Bug target/99842] New: " bergner at gcc dot gnu.org
2021-03-30 23:20 ` [Bug target/99842] " bergner at gcc dot gnu.org
2021-04-27 11:40 ` jakub at gcc dot gnu.org
2021-05-21 19:49 ` bergner at gcc dot gnu.org
2021-05-31 3:46 ` cvs-commit at gcc dot gnu.org [this message]
2021-06-17 22:04 ` cvs-commit at gcc dot gnu.org
2021-06-18 3:17 ` cvs-commit at gcc dot gnu.org
2021-06-18 20:19 ` bergner at gcc dot gnu.org
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