From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 4B0CB3898506; Wed, 7 Apr 2021 10:27:06 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 4B0CB3898506 From: "crazylht at gmail dot com" To: gcc-bugs@gcc.gnu.org Subject: [Bug rtl-optimization/99930] Failure to optimize floating point -abs(x) in nontrivial code at -O2/3 Date: Wed, 07 Apr 2021 10:27:05 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: rtl-optimization X-Bugzilla-Version: 11.0 X-Bugzilla-Keywords: missed-optimization X-Bugzilla-Severity: normal X-Bugzilla-Who: crazylht at gmail dot com X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-BeenThere: gcc-bugs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-bugs mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 07 Apr 2021 10:27:06 -0000 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D99930 --- Comment #7 from Hongtao.liu --- i'm testing 1 file changed, 30 insertions(+) gcc/combine.c | 30 ++++++++++++++++++++++++++++++ modified gcc/combine.c @@ -1811,6 +1811,33 @@ set_nonzero_bits_and_sign_copies (rtx x, const_rtx s= et, void *data) } } } + +/* Return true is reg is only defined by loading from constant pool. */ +static int +single_ref_from_constant_pool (rtx reg) +{ + gcc_assert (REG_P (reg)); + rtx_insn* insn; + rtx src, set; + + if (DF_REG_DEF_COUNT (REGNO (reg)) !=3D 1) + return 0; + insn =3D DF_REF_INSN (DF_REG_DEF_CHAIN (REGNO (reg))); + if (!insn) + return 0; + set =3D single_set (insn); + if (!set) + return 0; + src =3D SET_SRC (set); + + /* Constant pool. */ + if (!MEM_P (src) + || !SYMBOL_REF_P (XEXP (src, 0)) + || !CONSTANT_POOL_ADDRESS_P (XEXP (src, 0))) + return 0; + + return 1; +} /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are optionally insns that were previously combined into I3 or that will be @@ -1895,7 +1922,10 @@ can_combine_p (rtx_insn *insn, rtx_insn *i3, rtx_insn *pred ATTRIBUTE_UNUSED, something to tell them apart, e.g. different modes. For now, we forgo such complicated tests and simply disallow combining of USES of pseudo registers with any other USE. = */ + /* If the USE in INSN is only defined by loading from constant + pool, it must have identical value. */ if (REG_P (XEXP (elt, 0)) + && !single_ref_from_constant_pool (XEXP (elt, 0)) && GET_CODE (PATTERN (i3)) =3D=3D PARALLEL) { rtx i3pat =3D PATTERN (i3);=