From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 121684 invoked by alias); 10 Jan 2020 12:23:06 -0000 Mailing-List: contact gcc-cvs-wwwdocs-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-cvs-wwwdocs-owner@gcc.gnu.org Received: (qmail 121588 invoked by uid 9969); 10 Jan 2020 12:23:06 -0000 Date: Fri, 10 Jan 2020 12:23:00 -0000 Message-ID: <20200110122306.121584.qmail@sourceware.org> From: ktkachov@gcc.gnu.org To: gcc-cvs-wwwdocs@gcc.gnu.org Subject: gcc-wwwdocs branch master updated. a46c6a95e369659dc03c6052f49ff1061b37935d X-Git-Refname: refs/heads/master X-Git-Reftype: branch X-Git-Oldrev: 53f7b84d1c098cdda49e545b32ae050a04ca86c9 X-Git-Newrev: a46c6a95e369659dc03c6052f49ff1061b37935d X-SW-Source: 2020/txt/msg00002.txt This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "gcc-wwwdocs". The branch, master has been updated via a46c6a95e369659dc03c6052f49ff1061b37935d (commit) from 53f7b84d1c098cdda49e545b32ae050a04ca86c9 (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit a46c6a95e369659dc03c6052f49ff1061b37935d Author: Kyrylo Tkachov Date: Thu Nov 7 17:58:45 2019 +0000 [arm/aarch64] GCC 10 changes.html diff --git a/htdocs/gcc-10/changes.html b/htdocs/gcc-10/changes.html index d610826..8f49801 100644 --- a/htdocs/gcc-10/changes.html +++ b/htdocs/gcc-10/changes.html @@ -322,17 +322,102 @@ a work-in-progress.

New Targets and Target Specific Improvements

- +

AArch64 & arm

+
    +
  • The AArch64 and arm ports now support condition flag output constraints + in inline assembly, as indicated by the __GCC_ASM_FLAG_OUTPUTS__. + On arm this feature is only available for A32 and T32 targets. + Please refer to the documentation for more details.
    • +
+ +

AArch64

+
    +
  • The -mbranch-protection=pac-ret option now accepts the + optional argument +b-key extension to perform return address + signing with the B-key instead of the A-key. +
    • +
  • The Transactional Memory Extension is now supported through ACLE + intrinsics. It can be enabled through the +tme option + extension (for example, -march=armv8.5-a+tme). +
    • +
  • Initial autovectorization support for SVE2 has been added and can be + enabled through the +sve2 option extension (for example, + -march=armv8.5-a+sve2). Additional extensions can be enabled + through +sve2-sm4, +sve2=aes, + +sve2-sha3, +sve2-bitperm. +
    • +
  • A number of features from the Armv8.5-a are now supported through ACLE + intrinsics. These include: +
      +
    • The random number instructions that can be enabled + through the (already present in GCC 9.1) +rng option + extension.
      • +
    • Floating-point intrinsics to round to integer instructions from + Armv8.5-a when targeting -march=armv8.5-a or later.
      • +
    • Memory Tagging Extension intrinsics enabled through the + +memtag option extension.
      • +
    +
    • +
  • The option -moutline-atomics has been added to aid + deployment of the Large System Extensions (LSE) on GNU/Linux systems built + with a baseline architecture targeting Armv8-A. When the option is + specified code is emitted to detect the presence of LSE instructions at + runtime and use them for standard atomic operations. + For more information please refer to the documentation. +
    • +
  • + Support has been added for the following processors + (GCC identifiers in parentheses): +
      +
    • Arm Cortex-A77 (cortex-a77).
      • +
    • Arm Cortex-A76AE (cortex-a76ae).
      • +
    • Arm Cortex-A65 (cortex-a65).
      • +
    • Arm Cortex-A65AE (cortex-a65ae).
      • +
    • Arm Cortex-A34 (cortex-a34).
      • +
    + The GCC identifiers can be used + as arguments to the -mcpu or -mtune options, + for example: -mcpu=cortex-a77 or + -mtune=cortex-a65ae or as arguments to the equivalent target + attributes and pragmas. +
    • +
-

ARM

+

arm

  • Support for the FDPIC ABI has been added. It uses 64-bit function descriptors to represent pointers to functions, and enables code sharing on MMU-less systems. The corresponding target triple is arm-uclinuxfdpiceabi, and the C library is uclibc-ng.
    • +
  • Support has been added for the Arm EABI on NetBSD through the + arm*-*-netbsdelf-*eabi* triplet. +
    • +
  • The handling of 64-bit integer operations has been significantly reworked + and improved leading to improved performance and reduced stack usage when using + 64-bit integral data types. The option -mneon-for-64bits is now + deprecated and will be removed in a future release.
    • +
  • + Support has been added for the following processors + (GCC identifiers in parentheses): +
      +
    • Arm Cortex-A77 (cortex-a77).
      • +
    • Arm Cortex-A76AE (cortex-a76ae).
      • +
    • Arm Cortex-M35P (cortex-m35p).
      • +
    + The GCC identifiers can be used + as arguments to the -mcpu or -mtune options, + for example: -mcpu=cortex-a77 or + -mtune=cortex-m35p. +
    • +
  • Support has been extended for the ACLE + + data-processing intrinsics to include 32-bit SIMD, saturating arithmetic, + 16-bit multiplication and other related intrinsics aimed at DSP algorithm + optimization. +
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