From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1130) id D9478385B835; Thu, 9 Apr 2020 16:48:52 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D9478385B835 To: gcc-cvs-wwwdocs@gcc.gnu.org Subject: gcc-wwwdocs branch master updated. dadfa615891bdd36ea928e6d94d370009f300ff2 X-Git-Refname: refs/heads/master X-Git-Reftype: branch X-Git-Oldrev: cd4b2be81b0777a2221a8c5d77844910ad038e3d X-Git-Newrev: dadfa615891bdd36ea928e6d94d370009f300ff2 Message-Id: <20200409164852.D9478385B835@sourceware.org> Date: Thu, 9 Apr 2020 16:48:52 +0000 (GMT) From: Richard Sandiford X-BeenThere: gcc-cvs-wwwdocs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs-wwwdocs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 09 Apr 2020 16:48:53 -0000 This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "gcc-wwwdocs". The branch, master has been updated via dadfa615891bdd36ea928e6d94d370009f300ff2 (commit) from cd4b2be81b0777a2221a8c5d77844910ad038e3d (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit dadfa615891bdd36ea928e6d94d370009f300ff2 Author: Richard Sandiford Date: Thu Apr 9 16:00:19 2020 +0100 aarch64: Document SVE changes This seemed to flow more naturally if we organised things as: - improvements to existing features - new options - new extensions - new CPUs The patch also fixes up some missing tags flagged by xmllint. diff --git a/htdocs/gcc-10/changes.html b/htdocs/gcc-10/changes.html index 1c8d7a9f..61c767f4 100644 --- a/htdocs/gcc-10/changes.html +++ b/htdocs/gcc-10/changes.html @@ -237,6 +237,7 @@ a work-in-progress.

with the new attribute access. +

C

@@ -336,6 +337,7 @@ a work-in-progress.

causing an syntactic ambiguity. +
  • G++ can now detect modifying constant objects in constexpr evaluation (which is undefined behavior). @@ -452,6 +454,7 @@ a work-in-progress.

    For formatted input/output, if the explicit widths after the data-edit descriptors I, F and G have been omitted, default widths are used. +
  • A blank format item at the end of a format specification, i.e. nothing following the final comma, is allowed. Use the option @@ -478,6 +481,7 @@ a work-in-progress.

    CHARACTER expressions. Use the option -fdec.
  • +
  • Character type names in errors and warnings now include len in addition to kind; * is used for assumed @@ -516,38 +520,104 @@ a work-in-progress.

    AArch64

      -
    • The -mbranch-protection=pac-ret option now accepts the +
    • There have been several improvements related to the Scalable + Vector Extension (SVE): +
        +
      • The SVE ACLE types and intrinsics are now supported. They can + be accessed using the header file arm_sve.h. +
      • +
      • It is now possible to create fixed-length SVE types using + the arm_sve_vector_bits attribute. For example: +
        #if __ARM_FEATURE_SVE_BITS==512
        +typedef svint32_t vec512 __attribute__((arm_sve_vector_bits(512)));
        +typedef svbool_t pred512 __attribute__((arm_sve_vector_bits(512)));
        +#endif
        +
      • +
      • -mlow-precision-div, -mlow-precision-sqrt + and -mlow-precision-recip-sqrt now work for SVE. +
      • +
      • -msve-vector-bits=128 now generates + vector-length-specific code for little-endian targets. It continues + to generate vector-length-agnostic code for big-endian targets, + just as previous releases did for all targets. +
      • +
      • The vectorizer is now able to use extending loads and truncating + stores, including gather loads and scatter stores. +
      • +
      • The vectorizer now compares the cost of vectorizing with SVE + and vectorizing with Advanced SIMD and tries to pick the best one. + Previously it would always use SVE if possible. +
      • +
      • If a vector loop uses Advanced SIMD rather than SVE, the vectorizer + now considers using SVE to vectorize the left-over elements (the + “scalar tail” or “epilog”). +
      • +
      • Besides these specific points, there have been many general + improvements to the way that the vectorizer uses SVE. +
      • +
      +
    • +
    • The -mbranch-protection=pac-ret option now accepts the optional argument +b-key extension to perform return address signing with the B-key instead of the A-key.
    • +
    • The option -moutline-atomics has been added to aid + deployment of the Large System Extensions (LSE) on GNU/Linux systems built + with a baseline architecture targeting Armv8-A. When the option is + specified code is emitted to detect the presence of LSE instructions at + runtime and use them for standard atomic operations. + For more information please refer to the documentation. +
    • The Transactional Memory Extension is now supported through ACLE intrinsics. It can be enabled through the +tme option extension (for example, -march=armv8.5-a+tme).
    • -
    • Initial autovectorization support for SVE2 has been added and can be - enabled through the +sve2 option extension (for example, - -march=armv8.5-a+sve2). Additional extensions can be enabled - through +sve2-sm4, +sve2=aes, - +sve2-sha3, +sve2-bitperm. -
    • -
    • A number of features from the Armv8.5-a are now supported through ACLE +
    • A number of features from Armv8.5-A are now supported through ACLE intrinsics. These include:
      • The random number instructions that can be enabled through the (already present in GCC 9.1) +rng option extension.
      • Floating-point intrinsics to round to integer instructions from - Armv8.5-a when targeting -march=armv8.5-a or later.
      • + Armv8.5-A when targeting -march=armv8.5-a or later.
      • Memory Tagging Extension intrinsics enabled through the +memtag option extension.
    • -
    • The option -moutline-atomics has been added to aid - deployment of the Large System Extensions (LSE) on GNU/Linux systems built - with a baseline architecture targeting Armv8-A. When the option is - specified code is emitted to detect the presence of LSE instructions at - runtime and use them for standard atomic operations. - For more information please refer to the documentation. +
    • Similarly, the following Armv8.6-A features are now supported + through ACLE intrinsics: +
        +
      • The bfloat16 extension. This extension is enabled automatically + when Armv8.6-A is selected (such as by -march=armv8.6-a). + It can also be enabled for Armv8.2-A and later using the + +bf16 option extension. +
      • +
      • The Matrix Multiply extension. This extension is split into + three parts, one for each supported data type: +
          +
        • Support for 8-bit integer matrix multiply instructions. + This extension is enabled automatically when Armv8.6-A is + selected. It can also be enabled for Armv8.2-A and later using + the +i8mm option extension. +
        • +
        • Support for 32-bit floating-point matrix multiply instructions. + This extension can be enabled using the +f32mm + option extension, which also has the effect of enabling SVE. +
        • +
        • Support for 64-bit floating-point matrix multiply instructions. + This extension can be enabled using the +f64mm + option extension, which likewise has the effect of enabling SVE. +
        • +
        +
      • +
      +
    • +
    • SVE2 is now supported through ACLE intrinsics and (to a limited extent) + through autovectorization. It can be enabled through the +sve2 + option extension (for example, -march=armv8.5-a+sve2). + Additional extensions can be enabled through +sve2-sm4, + +sve2=aes, +sve2-sha3 and + +sve2-bitperm.
    • Support has been added for the following processors ----------------------------------------------------------------------- Summary of changes: htdocs/gcc-10/changes.html | 100 ++++++++++++++++++++++++++++++++++++++------- 1 file changed, 85 insertions(+), 15 deletions(-) hooks/post-receive -- gcc-wwwdocs