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To: gcc-cvs-wwwdocs@gcc.gnu.org
Subject: gcc-wwwdocs branch master updated.
d2f0049d34088519fa28c7c6c1ee62d239523258
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Date: Fri, 7 Aug 2020 09:49:35 +0000 (GMT)
From: Richard Sandiford
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The branch, master has been updated
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- Log -----------------------------------------------------------------
commit d2f0049d34088519fa28c7c6c1ee62d239523258
Author: Richard Sandiford
Date: Fri Aug 7 10:49:23 2020 +0100
Document A64FX support in GCC 10.3
diff --git a/htdocs/gcc-10/changes.html b/htdocs/gcc-10/changes.html
index b40f9a57..1a9e3ab7 100644
--- a/htdocs/gcc-10/changes.html
+++ b/htdocs/gcc-10/changes.html
@@ -1093,6 +1093,23 @@ known to be fixed in the 10.2 release. This list might not be
complete (that is, it is possible that some PRs that have been fixed
are not listed here).
+
+GCC 10.3
+
+Target Specific Changes
+
+AArch64
+
+ - GCC now supports the Fujitsu A64FX. The associated
-mcpu
+ and -mtune
options are -mcpu=a64fx
and
+ -mtune=a64fx
respectively. In particular,
+ -mcpu=a64fx
generates code for Armv8.2-A with SVE and
+ tunes the code for the A64FX. This includes tuning the SVE code,
+ although by default the code is still length-agnostic and so works for
+ all SVE implementations. Adding -msve-vector-bits=512
+ makes the code specific to 512-bit SVE.
+
+