gcc-wwwdocs branch master updated. d2f0049d34088519fa28c7c6c1ee62d239523258

gcc-wwwdocs branch master updated. d2f0049d34088519fa28c7c6c1ee62d239523258

[Richard Sandiford]

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- Log -----------------------------------------------------------------
commit d2f0049d34088519fa28c7c6c1ee62d239523258
Author: Richard Sandiford <richard.sandiford@arm.com>
Date:   Fri Aug 7 10:49:23 2020 +0100

    Document A64FX support in GCC 10.3

diff --git a/htdocs/gcc-10/changes.html b/htdocs/gcc-10/changes.html
index b40f9a57..1a9e3ab7 100644
--- a/htdocs/gcc-10/changes.html
+++ b/htdocs/gcc-10/changes.html
@@ -1093,6 +1093,23 @@ known to be fixed in the 10.2 release. This list might not be
 complete (that is, it is possible that some PRs that have been fixed
 are not listed here).</p>
 
+<!-- .................................................................. -->
+<h2 id="GCC10.3">GCC 10.3</h2>
+
+<h3>Target Specific Changes</h3>
+
+<h4>AArch64</h4>
+<ul>
+  <li>GCC now supports the Fujitsu A64FX.  The associated <code>-mcpu</code>
+  and <code>-mtune</code> options are <code>-mcpu=a64fx</code> and
+  <code>-mtune=a64fx</code> respectively.  In particular,
+  <code>-mcpu=a64fx</code> generates code for Armv8.2-A with SVE and
+  tunes the code for the A64FX.  This includes tuning the SVE code,
+  although by default the code is still length-agnostic and so works for
+  all SVE implementations.  Adding <code>-msve-vector-bits=512</code>
+  makes the code specific to 512-bit SVE.</li>
+</ul>
+
 <!-- .................................................................. -->
 
 </body>

-----------------------------------------------------------------------

Summary of changes:
 htdocs/gcc-10/changes.html | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)


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