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From: hongtao Liu <liuhongt@sourceware.org> To: gcc-cvs-wwwdocs@gcc.gnu.org Subject: gcc-wwwdocs branch master updated. e4d7ebb6579e169f6e17b1fb4b3c315ca6d9b1a0 Date: Fri, 16 Oct 2020 05:22:30 +0000 (GMT) [thread overview] Message-ID: <20201016052230.43FC53858D37@sourceware.org> (raw) This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "gcc-wwwdocs". The branch, master has been updated via e4d7ebb6579e169f6e17b1fb4b3c315ca6d9b1a0 (commit) from 8fa764914d32cf2cc218c5b10eb8d96c2d8b78e4 (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit e4d7ebb6579e169f6e17b1fb4b3c315ca6d9b1a0 Author: liuhongt <hongtao.liu@intel.com> Date: Fri Oct 16 13:18:11 2020 +0800 [GCC-11] Mention Intel HRESET, UINTR, AMX-TILE, AMX-BF16, AMX-INT8, -march=sapphirerapids and -march=alderlake. diff --git a/htdocs/gcc-11/changes.html b/htdocs/gcc-11/changes.html index 3c871c96..ac075966 100644 --- a/htdocs/gcc-11/changes.html +++ b/htdocs/gcc-11/changes.html @@ -217,6 +217,27 @@ a work-in-progress.</p> SERIALIZE intrinsics are available via the <code>-mserialize</code> compiler switch. </li> + <li>New ISA extension support for Intel HRESET was added to GCC. + HRESET intrinsics are available via the <code>-mhreset</code> + compiler switch. + </li> + <li>New ISA extension support for Intel UINTR was added to GCC. + UINTR intrinsics are available via the <code>-muintr</code> + compiler switch. + </li> + <li>New ISA extension support for Intel AMX-TILE, AMX-INT8, AMX-BF16 was + added to GCC. AMX-TILE, AMX-INT8, AMX-BF16 intrinsics are available + via the <code>-mamx-tile, -mamx-int8, -mamx-bf16</code> compiler switch. + </li> + <li>GCC now supports the Intel CPU named Sapphire Rapids through + <code>-march=sapphirerapids</code>. + The switch enables the MOVDIRI MOVDIR64B AVX512VP2INTERSECT ENQCMD CLDEMOTE + SERIALIZE PTWRITE WAITPKG TSXLDTRK AMT-TILE AMX-INT8 AMX-BF16 ISA extensions. + </li> + <li>GCC now supports the Intel CPU named Alderlake through + <code>-march=alderlake</code>. + The switch enables the CLDEMOTE PTWRITE WAITPKG SERIALIZE ISA extensions. + </li> </ul> ----------------------------------------------------------------------- Summary of changes: htdocs/gcc-11/changes.html | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) hooks/post-receive -- gcc-wwwdocs
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