From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1816) id 7596B3851C01; Tue, 26 Jan 2021 14:18:28 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 7596B3851C01 To: gcc-cvs-wwwdocs@gcc.gnu.org Subject: gcc-wwwdocs branch master updated. a19f3d62fd49243b50346814a0b9dc9f671dac73 X-Git-Refname: refs/heads/master X-Git-Reftype: branch X-Git-Oldrev: f7288746f791239cee98374ac1055f1b9c4d74fa X-Git-Newrev: a19f3d62fd49243b50346814a0b9dc9f671dac73 Message-Id: <20210126141828.7596B3851C01@sourceware.org> Date: Tue, 26 Jan 2021 14:18:28 +0000 (GMT) From: Kyrylo Tkachov X-BeenThere: gcc-cvs-wwwdocs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs-wwwdocs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 26 Jan 2021 14:18:28 -0000 This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "gcc-wwwdocs". The branch, master has been updated via a19f3d62fd49243b50346814a0b9dc9f671dac73 (commit) from f7288746f791239cee98374ac1055f1b9c4d74fa (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit a19f3d62fd49243b50346814a0b9dc9f671dac73 Author: Kyrylo Tkachov Date: Mon Jan 25 09:35:35 2021 +0000 arm,aarc64: add initial gcc-11/changes.html entries diff --git a/htdocs/gcc-11/changes.html b/htdocs/gcc-11/changes.html index 13a35e09..9d2e4f29 100644 --- a/htdocs/gcc-11/changes.html +++ b/htdocs/gcc-11/changes.html @@ -361,11 +361,60 @@ a work-in-progress.

New Targets and Target Specific Improvements

- +

AArch64 & arm

+
    +
  • A number of new CPUs are supported through arguments to the + -mcpu and -mtune options in both + the arm and aarch64 backends (GCC identifiers in parentheses): +
      +
    • Arm Cortex-A78 (cortex-a78).
      • +
    • Arm Cortex-A78AE (cortex-a78ae).
      • +
    • Arm Cortex-A78C (cortex-a78c).
      • +
    • Arm Cortex-X1 (cortex-x1).
      • +
    • Arm Neoverse V1 (neoverse-v1).
      • +
    • Arm Neoverse N2 (neoverse-n2).
      • +
    +
    • +
  • GCC can now auto-vectorize operations performing + addition, subtraction, multiplication and the accumulate/subtract variants + on complex numbers, taking advantage of the Advanced SIMD instructions in + the Armv8.3-a (AArch64/AArch32), SVE (AArch64), SVE2 (AArch64) and MVE + (AArch32 M-profile) instruction sets.
    • +
+ + +

AArch64

+
    +
  • In addition to the above, the following AArch64-only + CPUs are now supported: +
      +
    • Fujitsu A64FX (a64fx).
      • +
    • Arm Cortex-R82 (cortex-r82).
      • +
    +
    • +
  • The AArch64 Armv8-R architecture is now supported through the + -march=armv8-r option.
    • +
  • Mitigation against the + Straight-line Speculation vulnerability + is supported with the -mharden-sls= option. Please refer to the + documentation for usage instructions.
    • +
  • The availability of Advanced SIMD intrinsics available through the + arm_neon.h header is improved and GCC 11.0 supports the full + set of intrinsics defined by ACLE Q3 2020.
    • +
- +

arm

+
    +
  • Initial auto-vectorization is now available when targeting the MVE + instruction set.
    • +
  • GCC can now make use of the Low Overhead Branch instruction in Armv8.1-M + to optimize loop counters and checks.
    • +
  • The -mcpu=cortex-m55 option now supports the extensions + +nomve and +nomve.fp to control generation of + MVE and MVE floating-point instructions.
    • +
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