gcc-wwwdocs branch master updated. 67484a23c5f3eea55f06eb9fbc5b582b94db5037

gcc-wwwdocs branch master updated. 67484a23c5f3eea55f06eb9fbc5b582b94db5037

[H.J. Lu]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "gcc-wwwdocs".

The branch, master has been updated
       via  67484a23c5f3eea55f06eb9fbc5b582b94db5037 (commit)
      from  5c7ecfb5627e412a3d142d8dc212f4cd39b3b73f (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 67484a23c5f3eea55f06eb9fbc5b582b94db5037
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Sun Aug 29 10:11:50 2021 -0700

    x86-64: Document ABI changes for structures with a 64-bit vector
    
    TYPE_MODE of record and union depends on whether vector_mode_supported_p
    returns true or not.  x86-64 backend uses TYPE_MODE to decide how to pass
    a parameter and return a value in a function.  64-bit integer vectors
    were supported only by MMX and 64-bit float vector was supported only by
    3DNOW.  GCC 10.1 enabled 64-bit integer vectors without MMX by:
    
    commit dfa61b9ed06d71901c4c430caa89820972ad68fe
    Author: H.J. Lu <hongjiu.lu@intel.com>
    Date:   Wed May 15 15:02:54 2019 +0000
    
        i386: Allow MMX register modes in SSE registers
    
        In 64-bit mode, SSE2 can be used to emulate MMX instructions without
        3DNOW.  We can use SSE2 to support MMX register modes.
    
    GCC 10.4 is changed to diagnose this ABI change with -Wpsabi.
    
    GCC 11.1 enabled 64-bit float vector without 3DNOW by:
    
    commit 7c355156aa20eaec7401d7c66f6a6cfbe597abc2
    Author: Uros Bizjak <ubizjak@gmail.com>
    Date:   Mon May 11 11:16:31 2020 +0200
    
        i386: Vectorize basic V2SFmode operations [PR94913]
    
        Enable V2SFmode vectorization and vectorize V2SFmode PLUS,
        MINUS, MULT, MIN and MAX operations using XMM registers.
    
    GCC 11.3 is changed to diagnose this ABI change with -Wpsabi.

diff --git a/htdocs/gcc-10/changes.html b/htdocs/gcc-10/changes.html
index 5f386792..e3d8bed9 100644
--- a/htdocs/gcc-10/changes.html
+++ b/htdocs/gcc-10/changes.html
@@ -1155,6 +1155,24 @@ are not listed here).</p>
   via <code>-march=znver3</code>.
   </li>
 </ul>
+
+<!-- .................................................................. -->
+
+<h2 id="GCC10.4">GCC 10.4</h2>
+
+<h3>Target Specific Changes</h3>
+
+<h4>x86-64</h4>
+<ul>
+  <li>
+    <a id="x86_64_m64">The x86-64 ABI</a>
+    of passing and returning structures with a 64-bit integer vector
+    changed in GCC 10.1 when MMX is disabled.  Disabling MMX no longer
+    changes how they are passed nor returned.  This ABI change is now
+    diagnosed with <code>-Wpsabi</code>.
+  </li>
+</ul>
+
 <!-- .................................................................. -->
 
 </body>
diff --git a/htdocs/gcc-11/changes.html b/htdocs/gcc-11/changes.html
index c81f0e82..fbd1b8ba 100644
--- a/htdocs/gcc-11/changes.html
+++ b/htdocs/gcc-11/changes.html
@@ -1116,5 +1116,20 @@ are not listed here).</p>
 
 <!-- .................................................................. -->
 
+<h2><a name="11.3">GCC 11.3</a></h2>
+
+<h3>Target Specific Changes</h3>
+
+<h4>x86-64</h4>
+<ul>
+  <li>
+    <a id="x86_64_m64">The x86-64 ABI</a>
+    of passing and returning structure with a 64-bit single precision
+    vector changed in GCC 11.1 when 3DNOW is disabled.  Disabling 3DNOW
+    no longer changes how they are passed nor returned.  This ABI change
+    is now diagnosed with <code>-Wpsabi</code>.
+  </li>
+</ul>
+
 </body>
 </html>

-----------------------------------------------------------------------

Summary of changes:
 htdocs/gcc-10/changes.html | 18 ++++++++++++++++++
 htdocs/gcc-11/changes.html | 15 +++++++++++++++
 2 files changed, 33 insertions(+)


hooks/post-receive
-- 
gcc-wwwdocs