From mboxrd@z Thu Jan 1 00:00:00 1970
Return-Path:
Received: by sourceware.org (Postfix, from userid 1039)
id 639C23858413; Fri, 12 Nov 2021 20:08:04 +0000 (GMT)
DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 639C23858413
To: gcc-cvs-wwwdocs@gcc.gnu.org
Subject: gcc-wwwdocs branch master updated.
67484a23c5f3eea55f06eb9fbc5b582b94db5037
X-Git-Refname: refs/heads/master
X-Git-Reftype: branch
X-Git-Oldrev: 5c7ecfb5627e412a3d142d8dc212f4cd39b3b73f
X-Git-Newrev: 67484a23c5f3eea55f06eb9fbc5b582b94db5037
Message-Id: <20211112200804.639C23858413@sourceware.org>
Date: Fri, 12 Nov 2021 20:08:04 +0000 (GMT)
From: "H.J. Lu"
X-BeenThere: gcc-cvs-wwwdocs@gcc.gnu.org
X-Mailman-Version: 2.1.29
Precedence: list
List-Id: Gcc-cvs-wwwdocs mailing list
List-Unsubscribe: ,
List-Archive:
List-Help:
List-Subscribe: ,
X-List-Received-Date: Fri, 12 Nov 2021 20:08:04 -0000
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "gcc-wwwdocs".
The branch, master has been updated
via 67484a23c5f3eea55f06eb9fbc5b582b94db5037 (commit)
from 5c7ecfb5627e412a3d142d8dc212f4cd39b3b73f (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 67484a23c5f3eea55f06eb9fbc5b582b94db5037
Author: H.J. Lu
Date: Sun Aug 29 10:11:50 2021 -0700
x86-64: Document ABI changes for structures with a 64-bit vector
TYPE_MODE of record and union depends on whether vector_mode_supported_p
returns true or not. x86-64 backend uses TYPE_MODE to decide how to pass
a parameter and return a value in a function. 64-bit integer vectors
were supported only by MMX and 64-bit float vector was supported only by
3DNOW. GCC 10.1 enabled 64-bit integer vectors without MMX by:
commit dfa61b9ed06d71901c4c430caa89820972ad68fe
Author: H.J. Lu
Date: Wed May 15 15:02:54 2019 +0000
i386: Allow MMX register modes in SSE registers
In 64-bit mode, SSE2 can be used to emulate MMX instructions without
3DNOW. We can use SSE2 to support MMX register modes.
GCC 10.4 is changed to diagnose this ABI change with -Wpsabi.
GCC 11.1 enabled 64-bit float vector without 3DNOW by:
commit 7c355156aa20eaec7401d7c66f6a6cfbe597abc2
Author: Uros Bizjak
Date: Mon May 11 11:16:31 2020 +0200
i386: Vectorize basic V2SFmode operations [PR94913]
Enable V2SFmode vectorization and vectorize V2SFmode PLUS,
MINUS, MULT, MIN and MAX operations using XMM registers.
GCC 11.3 is changed to diagnose this ABI change with -Wpsabi.
diff --git a/htdocs/gcc-10/changes.html b/htdocs/gcc-10/changes.html
index 5f386792..e3d8bed9 100644
--- a/htdocs/gcc-10/changes.html
+++ b/htdocs/gcc-10/changes.html
@@ -1155,6 +1155,24 @@ are not listed here).
via -march=znver3
.
+
+
+
+GCC 10.4
+
+Target Specific Changes
+
+x86-64
+
+ -
+ The x86-64 ABI
+ of passing and returning structures with a 64-bit integer vector
+ changed in GCC 10.1 when MMX is disabled. Disabling MMX no longer
+ changes how they are passed nor returned. This ABI change is now
+ diagnosed with
-Wpsabi
.
+
+
+