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Subject: gcc-wwwdocs branch master updated.
17fded72af297e476b63fb51e6a53cdd4efa3c30
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Date: Wed, 2 Mar 2022 17:02:32 +0000 (GMT)
From: Kyrylo Tkachov
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This is an automated email from the git hooks/post-receive script. It was
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The branch, master has been updated
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- Log -----------------------------------------------------------------
commit 17fded72af297e476b63fb51e6a53cdd4efa3c30
Author: Kyrylo Tkachov
Date: Wed Feb 2 14:33:08 2022 +0000
Arm & AArch64 GCC 12 changes
diff --git a/htdocs/gcc-12/changes.html b/htdocs/gcc-12/changes.html
index e7c6ed8e..a3e46eeb 100644
--- a/htdocs/gcc-12/changes.html
+++ b/htdocs/gcc-12/changes.html
@@ -364,7 +364,44 @@ a work-in-progress.
New Targets and Target Specific Improvements
-
+AArch64 & arm
+
+ - Newer revisions of the Arm Architecture are supported as arguments to the
+
-march
option: armv8.7-a, armv8.8-a, armv9-a
.
+ - The Arm Cortex-A510 CPU is now supported through the
cortex-a510
+
argument to the -mcpu
and -mtune
options.
+
+ - GCC can now auto-vectorize operations performing sign-differing
+ dot-product operations, taking advantage of instructions in the Advanced SIMD
+ (AArch64/AArch32) and SVE (AArch64) instruction sets.
+
+
+
+AArch64
+
+ - A number of new CPUs are supported through the
-mcpu
and
+ -mtune
options (GCC identifiers in parentheses).
+
+ - Ampere-1 (
ampere1
).
+ - Arm Cortex-A710 (
cortex-a710
).
+ - Arm Cortex-X2 (
cortex-x2
).
+
+
+ - The 64-byte atomic load/store intrinsics to accelerator memory from the
+
+ 2020 Arm Architecture extensions are supported through the
+
+ls64
option extension.
+ - Initial code generation support is supported for hardware instructions
+ used to accelerate the
memcpy
,memmove
and
+ memset
standard functions. These instructions can be generated
+ when compiling with the +mops
option extension.
+ - The ACLE Advanced SIMD intrinsics accessible through the
+
arm_neon.h
header have been significantly reimplemented and
+ generate higher-performing code than previous GCC versions.
+ - The option
-mtune=neoverse-512tvb
is added to tune for Arm
+ Neoverse cores that have a total vector bandwidth of 512 bits. Please refer
+ to the documentation for more details.
+
AMD Radeon (GCN)
@@ -380,7 +417,14 @@ a work-in-progress.
-
+arm
+
+ - Support is added for accessing the stack canary value via the TLS register
+ through the
-fstack-protector-guard=tls
and
+ -mstack-protector-guard-offset=
options. This intended for use
+ in Linux kernel development. Please refer to the documentation for more
+ details.
+
-----------------------------------------------------------------------
Summary of changes:
htdocs/gcc-12/changes.html | 48 ++++++++++++++++++++++++++++++++++++++++++++--
1 file changed, 46 insertions(+), 2 deletions(-)
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