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To: gcc-cvs-wwwdocs@gcc.gnu.org
Subject: gcc-wwwdocs branch master updated. 8edbd72f42afcfc7c92099b9feaf42e5f0ccf11b
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Date: Thu, 23 Feb 2023 12:00:18 +0000 (GMT)
From: Kyrylo Tkachov
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This is an automated email from the git hooks/post-receive script. It was
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the project "gcc-wwwdocs".
The branch, master has been updated
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from 12b59ae29d88f7dcdd7e10fa66f2673283f599ba (commit)
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- Log -----------------------------------------------------------------
commit 8edbd72f42afcfc7c92099b9feaf42e5f0ccf11b
Author: Kyrylo Tkachov
Date: Wed Jan 25 11:49:56 2023 +0000
[arm/aarch64] Add GCC 13 release notes
diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html
index 5dbcc229..6034a8f9 100644
--- a/htdocs/gcc-13/changes.html
+++ b/htdocs/gcc-13/changes.html
@@ -52,7 +52,13 @@ a work-in-progress.
-fstrict-flex-arrays
.
-fanalyzer
is still only suitable for analyzing C code.
- In particular, using it on C++ is unlikely to give meaningful output.
+ In particular, using it on C++ is unlikely to give meaningful output.
+ In the arm port, support for the iWMMXt extensions, enabled through
+ -mcpu=iwmmxt
, has been deprecated and will be removed in a
+ future release. This includes support for the
+
+ iWMMXt built-in functions.
+
@@ -334,6 +340,8 @@ a work-in-progress.
AArch64
+ - The AArch64 target now supports Decimal Floating-point in the BID format
+ through the
libbid
library.
- A number of new CPUs are supported through the
-mcpu
and
-mtune
options (GCC identifiers in parentheses).
@@ -343,6 +351,22 @@ a work-in-progress.
- Arm Cortex-X3 (
cortex-x3
).
- Arm Neoverse V2 (
neoverse-v2
).
+ - Support has been added for the
armv9.1-a, armv9.2-a
and
+ armv9.3-a
arguments to the -march=
option.
+ - The
FEAT_LRCPC
feature is now supported by generating the
+ LDAPR
instructions for C and C++ atomic loads with an
+ acquire memory model. This is enabled when compiling with the
+ +rcpc
extension to -march
or a CPU target that
+ supports this feature.
+ - The
FEAT_CSSC
feature from the 2022 Arm Architecture
+ extensions is supported through the +cssc
extension option.
+ When enabled, scalar operations like integer minimum, maximum, absolute
+ value, count trailing zeroes (__builtin_ctz
), population
+ count (__builtin_popcount
) can be implemented in a
+ single instruction.
+ - The
FEAT_LSE2
feature is now supported through
+ libatomic
and provides lockless 16-byte atomics on systems
+ that implement it.
AMD Radeon (GCN)
@@ -356,8 +380,18 @@ a work-in-progress.
arm
- - The STAR-MC1 CPU is now supported through the
star-mc1
- argument to the -mcpu
and -mtune
options.
+ - A number of new CPUs are supported through the
-mcpu
and
+ -mtune
options (GCC identifiers in parentheses).
+
+ - STAR-MC1 (
star-mc1
).
+ - Arm Cortex-X1C (
cortex-x1c
).
+ - Arm Cortex-M85 (
cortex-m85
).
+
+
+ - Support has been added for the M-profile PACBTI extension that can help
+ harden the generated code against return-oriented and
+ jump-oriented attacks. It can be enabled through the
+
-mbranch-protection=
option.
-----------------------------------------------------------------------
Summary of changes:
htdocs/gcc-13/changes.html | 40 +++++++++++++++++++++++++++++++++++++---
1 file changed, 37 insertions(+), 3 deletions(-)
hooks/post-receive
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gcc-wwwdocs