From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <jianghc@sourceware.org>
Received: by sourceware.org (Postfix, from userid 7888)
	id 9D3613858D20; Mon, 30 Oct 2023 07:37:25 +0000 (GMT)
DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 9D3613858D20
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org;
	s=default; t=1698651445;
	bh=ZHxKssNSbOnmQCrTjIk4E9Qv0pUNv8JbPYbdGeG2D6g=;
	h=To:Subject:Date:From:From;
	b=WdfQKfhciXeR5fca6OtZ70UHMhMUMFbk8Ro2ScESNBpsFTDkTMYt7rYy+a2YT0IBC
	 ZJFYtSRWb9j75TYhSfHg2vViROFiNMS1B9++jruiTnKHEJoDi/ER2X2Y+bNiEVUisg
	 d71gPzJeD+26Yf7jgzy2mEPa138ojLQkm5yi7tqE=
To: gcc-cvs-wwwdocs@gcc.gnu.org
Subject: gcc-wwwdocs branch master updated. fcd40a093f9e311cf4ff1bf3910f69f261a32e79
X-Git-Refname: refs/heads/master
X-Git-Reftype: branch
X-Git-Oldrev: 76857f1aae9af9d04ea401004f29c988a2593140
X-Git-Newrev: fcd40a093f9e311cf4ff1bf3910f69f261a32e79
Message-Id: <20231030073725.9D3613858D20@sourceware.org>
Date: Mon, 30 Oct 2023 07:37:25 +0000 (GMT)
From: Haochen Jiang <jianghc@sourceware.org>
List-Id: <gcc-cvs-wwwdocs.sourceware.org>

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "gcc-wwwdocs".

The branch, master has been updated
       via  fcd40a093f9e311cf4ff1bf3910f69f261a32e79 (commit)
      from  76857f1aae9af9d04ea401004f29c988a2593140 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit fcd40a093f9e311cf4ff1bf3910f69f261a32e79
Author: Haochen Jiang <haochen.jiang@intel.com>
Date:   Mon Oct 23 10:14:29 2023 +0800

    gcc-13/14: Mention Intel new ISA and march support

diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html
index 10c54689..8ef3d639 100644
--- a/htdocs/gcc-13/changes.html
+++ b/htdocs/gcc-13/changes.html
@@ -579,13 +579,13 @@ You may also want to check out our
   </li>
   <li>GCC now supports the Intel CPU named Sierra Forest through
     <code>-march=sierraforest</code>.
-    The switch enables the AVX-IFMA, AVX-VNNI-INT8, AVX-NE-CONVERT and
-    CMPccXADD ISA extensions.
+    The switch enables the AVX-IFMA, AVX-VNNI-INT8, AVX-NE-CONVERT, CMPccXADD,
+    ENQCMD and UINTR ISA extensions.
   </li>
   <li>GCC now supports the Intel CPU named Grand Ridge through
     <code>-march=grandridge</code>.
-    The switch enables the AVX-IFMA, AVX-VNNI-INT8, AVX-NE-CONVERT, CMPccXADD
-    and RAO-INT ISA extensions.
+    The switch enables the AVX-IFMA, AVX-VNNI-INT8, AVX-NE-CONVERT, CMPccXADD,
+    ENQCMD, UINTR and RAO-INT ISA extensions.
   </li>
   <li>GCC now supports the Intel CPU named Emerald Rapids through
     <code>-march=emeraldrapids</code>.
diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html
index a20499e9..5611fc4f 100644
--- a/htdocs/gcc-14/changes.html
+++ b/htdocs/gcc-14/changes.html
@@ -201,6 +201,10 @@ a work-in-progress.</p>
 
 <h3 id="x86">IA-32/x86-64</h3>
 <ul>
+  <li>New compiler option <code>-m[no-]evex512</code> was added.
+      The compiler switch enables/disables 512 bit vector and 64 bit mask
+      register. It will be default on if AVX512F is enabled.
+  </li>
   <li>New ISA extension support for Intel AVX-VNNI-INT16 was added.
       AVX-VNNI-INT16 intrinsics are available via the <code>-mavxvnniint16</code>
       compiler switch.
@@ -217,6 +221,16 @@ a work-in-progress.</p>
       SM4 intrinsics are available via the <code>-msm4</code>
       compiler switch.
   </li>
+  <li>New ISA extension support for Intel USER_MSR was added.
+      USER_MSR intrinsics are available via the <code>-muser_msr</code>
+      compiler switch.
+  </li>
+  <li>GCC now supports the Intel CPU named Clearwater Forest through
+    <code>-march=clearwaterforest</code>.
+    Based on Sierra Forest, the switch further enables the AVX-VNNI-INT16,
+    SHA512, SM3, SM4, USER_MSR and PREFETCHI ISA extensions.
+    extensions.
+  </li>
   <li>GCC now supports the Intel CPU named Arrow Lake through
     <code>-march=arrowlake</code>.
     Based on Alder Lake, the switch further enables the AVX-IFMA,
@@ -231,6 +245,11 @@ a work-in-progress.</p>
     <code>-march=lunarlake</code>.
     Lunar Lake is based on Arrow Lake S.
   </li>
+  <li>GCC now supports the Intel CPU named Panther Lake through
+    <code>-march=pantherlake</code>.
+    Based on Arrow Lake S, the switch further enables the PREFETCHI ISA
+    extensions.
+  </li>
 </ul>
 
 <!-- <h3 id="mips">MIPS</h3> -->

-----------------------------------------------------------------------

Summary of changes:
 htdocs/gcc-13/changes.html |  8 ++++----
 htdocs/gcc-14/changes.html | 19 +++++++++++++++++++
 2 files changed, 23 insertions(+), 4 deletions(-)


hooks/post-receive
-- 
gcc-wwwdocs