From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 7888) id 5744F3858C62; Wed, 27 Dec 2023 08:30:18 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 5744F3858C62 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1703665818; bh=UfwQr+L/LDolvdRCjp4ql3vj73YI86qwXXF7AIRcixg=; h=To:Subject:Date:From:From; b=KH38D25fY4rkFJxPiJuvRtGw6uwlwBWjXHMhhph2ih3N5xWuZqdHmdaoPLJs6GA/M hvCEq7Va4GNhsjY7jfYdkxwvGouKNhkU92G9cPRchREbPhu4eQiJimuivLhBWPPxzQ hOQpPBponAuvJuopzV1u/bY1nL6hFTig92je7MRU= To: gcc-cvs-wwwdocs@gcc.gnu.org Subject: gcc-wwwdocs branch master updated. 75418ca06871952152d541501e410ce54c08214a X-Git-Refname: refs/heads/master X-Git-Reftype: branch X-Git-Oldrev: 0d8105fd15b33980886283869e980f60f2ca9f04 X-Git-Newrev: 75418ca06871952152d541501e410ce54c08214a Message-Id: <20231227083018.5744F3858C62@sourceware.org> Date: Wed, 27 Dec 2023 08:30:18 +0000 (GMT) From: Haochen Jiang List-Id: This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "gcc-wwwdocs". The branch, master has been updated via 75418ca06871952152d541501e410ce54c08214a (commit) from 0d8105fd15b33980886283869e980f60f2ca9f04 (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit 75418ca06871952152d541501e410ce54c08214a Author: Haochen Jiang Date: Wed Dec 27 16:30:05 2023 +0800 gcc-13/14: Mention recent update for x86_64 backend Mention AVX10.1 support, APX support and Xeon Phi deprecate in GCC 14. Also adjust documentation in GCC 13. diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html index d3bacc16..b4b1a39a 100644 --- a/htdocs/gcc-13/changes.html +++ b/htdocs/gcc-13/changes.html @@ -543,24 +543,28 @@ You may also want to check out our __bf16 type to x86 psABI. Users need to adjust their AVX512BF16-related source code when upgrading GCC12 to GCC13. -
  • New ISA extension support for Intel AVX-IFMA was added. - AVX-IFMA intrinsics are available via the -mavxifma +
  • New ISA extension support for Intel AMX-COMPLEX was added. + AMX-COMPLEX intrinsics are available via the -mamx-complex compiler switch.
    • -
  • New ISA extension support for Intel AVX-VNNI-INT8 was added. - AVX-VNNI-INT8 intrinsics are available via the -mavxvnniint8 +
  • New ISA extension support for Intel AMX-FP16 was added. + AMX-FP16 intrinsics are available via the -mamx-fp16 + compiler switch. +
    • +
  • New ISA extension support for Intel AVX-IFMA was added. + AVX-IFMA intrinsics are available via the -mavxifma compiler switch.
  • New ISA extension support for Intel AVX-NE-CONVERT was added. AVX-NE-CONVERT intrinsics are available via the -mavxneconvert compiler switch.
    • -
  • New ISA extension support for Intel CMPccXADD was added. - CMPccXADD intrinsics are available via the -mcmpccxadd +
  • New ISA extension support for Intel AVX-VNNI-INT8 was added. + AVX-VNNI-INT8 intrinsics are available via the -mavxvnniint8 compiler switch.
    • -
  • New ISA extension support for Intel AMX-FP16 was added. - AMX-FP16 intrinsics are available via the -mamx-fp16 +
  • New ISA extension support for Intel CMPccXADD was added. + CMPccXADD intrinsics are available via the -mcmpccxadd compiler switch.
  • New ISA extension support for Intel PREFETCHI was added. @@ -571,10 +575,6 @@ You may also want to check out our RAO-INT intrinsics are available via the -mraoint compiler switch.
    • -
  • New ISA extension support for Intel AMX-COMPLEX was added. - AMX-COMPLEX intrinsics are available via the -mamx-complex - compiler switch. -
  • GCC now supports the Intel CPU named Raptor Lake through -march=raptorlake. Raptor Lake is based on Alder Lake. @@ -585,13 +585,13 @@ You may also want to check out our
  • GCC now supports the Intel CPU named Sierra Forest through -march=sierraforest. - The switch enables the AVX-IFMA, AVX-VNNI-INT8, AVX-NE-CONVERT, CMPccXADD, - ENQCMD and UINTR ISA extensions. + Based on ISA extensions enabled on Alder Lake, the switch further enables + the AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8, CMPccXADD, ENQCMD and UINTR + ISA extensions.
  • GCC now supports the Intel CPU named Grand Ridge through -march=grandridge. - The switch enables the AVX-IFMA, AVX-VNNI-INT8, AVX-NE-CONVERT, CMPccXADD, - ENQCMD, UINTR and RAO-INT ISA extensions. + Grand Ridge is based on Sierra Forest.
  • GCC now supports the Intel CPU named Emerald Rapids through -march=emeraldrapids. @@ -599,11 +599,13 @@ You may also want to check out our
  • GCC now supports the Intel CPU named Granite Rapids through -march=graniterapids. - The switch enables the AMX-FP16 and PREFETCHI ISA extensions. + Based on Sapphire Rapids, the switch further enables the AMX-FP16 and + PREFETCHI ISA extensions.
  • GCC now supports the Intel CPU named Granite Rapids D through -march=graniterapids-d. - The switch enables the AMX-FP16, PREFETCHI and AMX-COMPLEX ISA extensions. + Based on Granite Rapids, the switch further enables the AMX-COMPLEX ISA + extensions.
  • GCC now supports AMD CPUs based on the znver4 core via -march=znver4. The switch makes GCC consider diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html index 24e6409a..4b83037a 100644 --- a/htdocs/gcc-14/changes.html +++ b/htdocs/gcc-14/changes.html @@ -320,8 +320,18 @@ a work-in-progress.

    IA-32/x86-64

    • New compiler option -m[no-]evex512 was added. - The compiler switch enables/disables 512 bit vector and 64 bit mask - register. It will be default on if AVX512F is enabled. + The compiler switch enables/disables 512-bit vector. + It will be default on if AVX512F is enabled. +
      • +
    • Part of new feature support for Intel APX was added, including EGPR, + NDD, PPX and PUSH2POP2. APX support is available via the + -mapxf compiler switch. +
      • +
    • New ISA extension support for Intel AVX10.1 was added. + AVX10.1 intrinsics are available via the -mavx10.1 or + -mavx10.1-256 compiler switch with 256-bit vector size + support. 512-bit vector size support for AVX10.1 intrinsics are + available via the -mavx10.1-512 compiler switch.
    • New ISA extension support for Intel AVX-VNNI-INT16 was added. AVX-VNNI-INT16 intrinsics are available via the -mavxvnniint16 @@ -346,13 +356,12 @@ a work-in-progress.

    • GCC now supports the Intel CPU named Clearwater Forest through -march=clearwaterforest. Based on Sierra Forest, the switch further enables the AVX-VNNI-INT16, - SHA512, SM3, SM4, USER_MSR and PREFETCHI ISA extensions. - extensions. + PREFETCHI, SHA512, SM3, SM4 and USER_MSR ISA extensions.
    • GCC now supports the Intel CPU named Arrow Lake through -march=arrowlake. Based on Alder Lake, the switch further enables the AVX-IFMA, - AVX-VNNI-INT8, AVX-NE-CONVERT and CMPccXADD ISA extensions. + AVX-NE-CONVERT, AVX-VNNI-INT8 and CMPccXADD ISA extensions.
    • GCC now supports the Intel CPU named Arrow Lake S through -march=arrowlake-s. @@ -368,6 +377,14 @@ a work-in-progress.

      Based on Arrow Lake S, the switch further enables the PREFETCHI ISA extensions.
      • +
    • Xeon Phi CPUs support (a.k.a. Knight Landing and Knight Mill) are marked + as deprecated. GCC will emit a warning when using the + -mavx5124fmaps, -mavx5124vnniw, + -mavx512er, -mavx512pf, + -mprefetchwt1, -march=knl, + -march=knm, -mtune=knl or -mtune=knm + compiler switches. Support will be removed in GCC 15. +
    ----------------------------------------------------------------------- Summary of changes: htdocs/gcc-13/changes.html | 38 ++++++++++++++++++++------------------ htdocs/gcc-14/changes.html | 27 ++++++++++++++++++++++----- 2 files changed, 42 insertions(+), 23 deletions(-) hooks/post-receive -- gcc-wwwdocs