From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1816) id 958EE3858C32; Tue, 2 Apr 2024 10:01:28 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 958EE3858C32 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1712052088; bh=DZX4t7Zj7OdiR4SK1fOscB1UcwHF/kcyRigH4oigqtA=; h=To:Subject:Date:From:From; b=q8f/DaeJmZ/WG1ozf3h2a/S6UCoDQKQWOh2K8paG0C2NjFexmrVGpo3vtmHmGVSjU BYDiGI32AbGiZaT5TFnVAzsUBJa2ttnshnm9zaBbIAGX6E3C9ZjrHm4ojEN/i4ogOE xyfXtdkmDasp3SMkkP99fk8Y86PI1JSN+G+mYsq0= To: gcc-cvs-wwwdocs@gcc.gnu.org Subject: gcc-wwwdocs branch master updated. 501aef9bacc3842d0b7d022a4333c9d71d419d4d X-Git-Refname: refs/heads/master X-Git-Reftype: branch X-Git-Oldrev: 4f5550e76b8bd55d15479f9556bd25280e7244e0 X-Git-Newrev: 501aef9bacc3842d0b7d022a4333c9d71d419d4d Message-Id: <20240402100128.958EE3858C32@sourceware.org> Date: Tue, 2 Apr 2024 10:01:28 +0000 (GMT) From: Kyrylo Tkachov List-Id: This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "gcc-wwwdocs". The branch, master has been updated via 501aef9bacc3842d0b7d022a4333c9d71d419d4d (commit) from 4f5550e76b8bd55d15479f9556bd25280e7244e0 (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit 501aef9bacc3842d0b7d022a4333c9d71d419d4d Author: Kyrylo Tkachov Date: Mon Mar 25 15:11:21 2024 +0000 AArch64 GCC 14.1 changes.html entry diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html index 880b9195..9fd224c1 100644 --- a/htdocs/gcc-14/changes.html +++ b/htdocs/gcc-14/changes.html @@ -338,7 +338,94 @@ a work-in-progress.

New Targets and Target Specific Improvements

- +

AArch64

+ +
    +
  • A number of new CPUs are supported through the -mcpu and + -mtune options (GCC identifiers in parentheses). +
      +
    • Ampere-1B (ampere1b).
      • +
    • Arm Cortex-A520 (cortex-a520).
      • +
    • Arm Cortex-A720 (cortex-a720).
      • +
    • Arm Cortex-X4 (cortex-x4).
      • +
    • Microsoft Cobalt-100 (cobalt-100).
      • +
    • +
  • Additionally, the identifiers generic, + generic-armv8-a and generic-armv9-a are added + as arguments to -mcpu= and -mtune= to optimize + code generation aimed at a good blend of CPUs of a particular architecture + version. These tunings are also used as the default optimization targets + when compiling with the -march=armv8-a or + -march=armv9-a options and their point releases e.g. + -march=armv8.2-a or -march=armv9.3-a.
    • + +
  • New features in the Arm architecture are supported in a number of ways: +
      +
    • Support is added for the Arm Streaming Matrix Extensions SME and SME2 + through the +sme and +sme2 extensions to + -march=. In particular, this includes support for the Beta state + of the + SME ACLE in the form of a new intrinsics arm_sme.h + intrinsics header and a number of new keyword attributes to manage use + of the new Streaming SVE state. For more information please refer to the + ACLE documentation.
      • +
    • Libatomic is updated to implement 128-bit atomic operations + locklessly on systems with FEAT_LSE2.
      • +
    • Support for FEAT_LRCPC3 is added through ACLE intrinsics in + arm_neon.h header and enabled through the +rcpc3 + extension to -march=.
      • +
    • +
  • As well as numerous AArch64 code generation improvements, the following + optimization enhancements are noteworthy: +
      +
    • A new AArch64-specific register allocation pass is added. + It runs in addition to standard register allocation. + The pass's main purpose is to make use of strided vector register + operands in SME instructions. However, it can also remove + redundant moves in normal Advanced SIMD and SVE code. + The pass is controlled by the new option -mearly-ra= + that takes the arguments all, strided, none. + -mearly-ra=all is enabled by default at optimization levels + -O2 and above.
      • +
    • A new optimization pass to fuse loads and stores to adjacent memory + locations into load and store-pair AArch64 instructions. The pass is + enabled by default when compiling with optimization and runs twice in the + optimization pipeline: before and after register allocation. This can be + controlled with the options -mearly-ldp-fusion and + -mlate-ldp-fusion.
      • +
    • +
  • Conformance with the ACLE specification is improved and a number of + features aimed at helping developers deploy Arm architecture features are + added: +
      +
    • Support for the Beta version of the + + Function Multiversioning Specification. This feature provides + facilities to annotate functions with attributes that allow the compiler + to generate multiple versions of the function, selected at runtime based + on the architecture features available in the system. Please refer to + the ACLE specification for more details.
      • +
    • Support for more ACLE intrinsics in the arm_acle.h + header, including the + + Memory prefetch intrinsics and the + + Special register intrinsics. + This also includes intrinsics for the extension to 128-bit system + registers, enabled through the +d128 extension to + -march=.
      • +
    • Intrinsics enabled by the +dotprod, +fp16, + +fp16fml, +i8mm, +sha3 and + +sm4 extensions to -march= no longer require + -march=armv8.2-a or higher to be specified. Likewise, the + intrinsics enabled by +memtag no longer require + -march=armv8.5-a.
      • +
    • +
  • The option -mtp= is now supported for changing the TPIDR + register used for TLS accesses. For more details please refer to the + + documentation.
    • +

AMD Radeon (GCN)

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