From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2093) id BD05F385840B; Thu, 11 Apr 2024 07:17:18 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org BD05F385840B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1712819838; bh=6b7aYAQy972VcDsTLAfTrcIuI18P3qsDo9IvqYQ48VI=; h=To:Subject:Date:From:From; b=bCfbikmoODXrADFp0vifE4Ofhmaq7dglbKu/AS6pw/OB3t6utC+2AMaGHamDeX/Dy SgyBMEPHfV0vDUE5aE0Wnl3+ufQJw0hnkupCKoYIR+/YNijjDyzNkwx1krzxRHJb8L 55VVBbXi8OgY4q3MadRMJBwmtxVSeSeKRyy7DO0c= To: gcc-cvs-wwwdocs@gcc.gnu.org Subject: gcc-wwwdocs branch master updated. edc6411ab81dde8a0621ee706e6ff951be645922 X-Git-Refname: refs/heads/master X-Git-Reftype: branch X-Git-Oldrev: d65752191baaa137eb6d604b802e7b9170a39752 X-Git-Newrev: edc6411ab81dde8a0621ee706e6ff951be645922 Message-Id: <20240411071718.BD05F385840B@sourceware.org> Date: Thu, 11 Apr 2024 07:17:18 +0000 (GMT) From: Kito Cheng List-Id: This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "gcc-wwwdocs". The branch, master has been updated via edc6411ab81dde8a0621ee706e6ff951be645922 (commit) from d65752191baaa137eb6d604b802e7b9170a39752 (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit edc6411ab81dde8a0621ee706e6ff951be645922 Author: Kito Cheng Date: Mon Apr 8 22:40:31 2024 +0800 gcc-14: Add RISC-V changes Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html index 5c2439ab..14301157 100644 --- a/htdocs/gcc-14/changes.html +++ b/htdocs/gcc-14/changes.html @@ -853,7 +853,162 @@ __asm (".global __flmap_lock" "\n\t" - +

RISC-V

+
    +
  • The SLP and loop vectorizer are now enabled for RISC-V when the vector + extension is enabled, thanks to Ju-Zhe Zhong from + RiVAI, + Pan Li from Intel, and Robin Dapp + from Ventana Micro for + contributing most of the implementation!
    • +
  • The -mrvv-max-lmul= option has been introduced for + performance tuning of the loop vectorizer. The default value is + -mrvv-max-lmul=m1, which limits the maximum LMUL to 1. + The -mrvv-max-lmul=dynamic setting can dynamically select + the maximum LMUL value based on register pressure.
    • +
  • Atomic code generation has been improved and is now in conformance with + the latest psABI specification, thanks to Patrick O'Neill from + Rivos.
    • +
  • Support for the vector intrinsics as specified in + + version 1.0 of the RISC-V vector intrinsic specification.
    • +
  • Support for the experimental vector crypto intrinsics as specified in + + RISC-V vector intrinsic specification, thanks to Feng Wang et al. + from ESWIN Computing
    • +
  • Support for the T-head vector intrinsics.
    • +
  • Support for the scalar bitmanip and scalar crypto intrinsics, thanks to + Liao Shihua from PLCT.
    • +
  • Support for the large code model via option -mcmodel=large, + thanks to Kuan-Lin Chen from + Andes Technology.
    • +
  • Support for the standard vector calling convention variant, thanks to + Lehua Ding from RiVAI.
    • +
  • Supports the target attribute, which allows users to compile + a function with specific extensions.
    • +
  • -march= option no longer requires the architecture string + to be in canonical order, with only a few constraints remaining: the + architecture string must start with rv[32|64][i|g|e], and + must use an underscore as the separator after a multi-letter extension. +
    • +
  • -march=help option has been introduced to dump all + supported extensions.
    • +
  • Added experimental support for the -mrvv-vector-bits=zvl + option and the riscv_rvv_vector_bits attribute, which + specify a fixed length for scalable vector types. This option is + optimized for specific vector core implementations; however, the code + generated with this option is NOT portable between the core with + different VLEN, + thanks to Pan Li from Intel. +
    • +
  • Support for TLS descriptors has been introduced, which can be enabled by + the -mtls-dialect=desc option. The default behavior can be + configured with --with-tls=[trad|desc].
    • +
  • Support for the TLS descriptors, this can be enabled by + -mtls-dialect=desc and the default behavior can be configure + by --with-tls=[trad|desc], and this feature require glibc 2.40, + thanks to Tatsuyuki Ishi from + Blue Whale Systems +
    • +
  • Support for the following standard extensions has been added: +
      +
    • Vector crypto extensions: +
        +
      • Zvbb
        • +
      • Zvkb
        • +
      • Zvbc
        • +
      • Zvkg
        • +
      • Zvkned
        • +
      • Zvkhna
        • +
      • Zvkhnb
        • +
      • Zvksed
        • +
      • Zvksh
        • +
      • Zvkn
        • +
      • Zvknc
        • +
      • Zvkng
        • +
      • Zvks
        • +
      • Zvksc
        • +
      • Zvksg
        • +
      • Zvkt
        • +
      +
      • +
    • Code size reduction extensions: +
        +
      • Zca
        • +
      • Zcb
        • +
      • Zce
        • +
      • Zcf
        • +
      • Zcd
        • +
      • Zcmp
        • +
      • Zcmt
        • +
      +
      • +
    • Zicond
      • +
    • Zfa
      • +
    • Ztso
      • +
    • Zvfbfmin
      • +
    • Zvfhmin
      • +
    • Zvfh
      • +
    • Za64rs
      • +
    • Za128rs
      • +
    • Ziccif
      • +
    • Ziccrse
      • +
    • Ziccamoa
      • +
    • Zicclsm
      • +
    • Zic64b
      • +
    • Smaia
      • +
    • Smepmp
      • +
    • Smstateen
      • +
    • Ssaia
      • +
    • Sscofpmf
      • +
    • Ssstateen
      • +
    • Sstc
      • +
    • Svinval
      • +
    • Svnapot
      • +
    • Svpbmt
      • +
    +
    • +
  • Support for the following vendor extensions has been added: +
      +
    • T-Head: +
        +
      • XTheadVector
        • +
      +
      • +
    • CORE-V: +
        +
      • XCVmac
        • +
      • XCValu
        • +
      • XCVelw
        • +
      • XCVsimd
        • +
      • XCVbi
        • +
      +
      • +
    • Ventana Micro: +
        +
      • XVentanaCondops
        • +
      +
      • +
    +
    • +
  • The following new CPUs are supported through the -mcpu + option (GCC identifiers in parentheses). +
      +
    • SiFive's X280 (sifive-x280).
      • +
    • SiFive's P450 (sifive-p450).
      • +
    • SiFive's P670 (sifive-p670).
      • +
    +
    • +
  • The following new CPUs are supported through the -mtune + option (GCC identifiers in parentheses). +
      +
    • Generic out-of-order core (generic-ooo).
      • +
    • SiFive's P400 series (sifive-p400-series).
      • +
    • SiFive's P600 series (sifive-p600-series).
      • +
    • XiangShan's Nanhu microarchitecture (xiangshan-nanhu).
      • +
    +
    • +
----------------------------------------------------------------------- Summary of changes: htdocs/gcc-14/changes.html | 157 ++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 156 insertions(+), 1 deletion(-) hooks/post-receive -- gcc-wwwdocs