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* [gcc r10-7256] [ARM][GCC][2/4x]: MVE intrinsics with quaternary operands.
@ 2020-03-18 16:59 Kyrylo Tkachov
0 siblings, 0 replies; only message in thread
From: Kyrylo Tkachov @ 2020-03-18 16:59 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:8eb3b6b9cf2e285450fc5efc98a63cf717d2b002
commit r10-7256-g8eb3b6b9cf2e285450fc5efc98a63cf717d2b002
Author: Srinath Parvathaneni <srinath.parvathaneni@arm.com>
Date: Wed Mar 18 16:58:10 2020 +0000
[ARM][GCC][2/4x]: MVE intrinsics with quaternary operands.
This patch supports following MVE ACLE intrinsics with quaternary operands.
vabdq_m_s8, vabdq_m_s32, vabdq_m_s16, vabdq_m_u8, vabdq_m_u32, vabdq_m_u16, vaddq_m_n_s8, vaddq_m_n_s32, vaddq_m_n_s16, vaddq_m_n_u8, vaddq_m_n_u32, vaddq_m_n_u16, vaddq_m_s8, vaddq_m_s32, vaddq_m_s16, vaddq_m_u8, vaddq_m_u32, vaddq_m_u16, vandq_m_s8, vandq_m_s32, vandq_m_s16, vandq_m_u8, vandq_m_u32, vandq_m_u16, vbicq_m_s8, vbicq_m_s32, vbicq_m_s16, vbicq_m_u8, vbicq_m_u32, vbicq_m_u16, vbrsrq_m_n_s8, vbrsrq_m_n_s32, vbrsrq_m_n_s16, vbrsrq_m_n_u8, vbrsrq_m_n_u32, vbrsrq_m_n_u16, vcaddq_rot270_m_s8, vcaddq_rot270_m_s32, vcaddq_rot270_m_s16, vcaddq_rot270_m_u8, vcaddq_rot270_m_u32, vcaddq_rot270_m_u16, vcaddq_rot90_m_s8, vcaddq_rot90_m_s32, vcaddq_rot90_m_s16, vcaddq_rot90_m_u8, vcaddq_rot90_m_u32, vcaddq_rot90_m_u16, veorq_m_s8, veorq_m_s32, veorq_m_s16, veorq_m_u8, veorq_m_u32, veorq_m_u16, vhaddq_m_n_s8, vhaddq_m_n_s32, vhaddq_m_n_s16, vhaddq_m_n_u8, vhaddq_m_n_u32, vhaddq_m_n_u16, vhaddq_m_s8, vhaddq_m_s32, vhaddq_m_s16, vhaddq_m_u8, vhaddq_m_u32, vhaddq_m_u16, vhcaddq_rot270_m_s8, vhcaddq_rot270_m_s32, vhcaddq_rot270_m_s16, vhcaddq_rot90_m_s8, vhcaddq_rot90_m_s32, vhcaddq_rot90_m_s16, vhsubq_m_n_s8, vhsubq_m_n_s32, vhsubq_m_n_s16, vhsubq_m_n_u8, vhsubq_m_n_u32, vhsubq_m_n_u16, vhsubq_m_s8, vhsubq_m_s32, vhsubq_m_s16, vhsubq_m_u8, vhsubq_m_u32, vhsubq_m_u16, vmaxq_m_s8, vmaxq_m_s32, vmaxq_m_s16, vmaxq_m_u8, vmaxq_m_u32, vmaxq_m_u16, vminq_m_s8, vminq_m_s32, vminq_m_s16, vminq_m_u8, vminq_m_u32, vminq_m_u16, vmladavaq_p_s8, vmladavaq_p_s32, vmladavaq_p_s16, vmladavaq_p_u8, vmladavaq_p_u32, vmladavaq_p_u16, vmladavaxq_p_s8, vmladavaxq_p_s32, vmladavaxq_p_s16, vmlaq_m_n_s8, vmlaq_m_n_s32, vmlaq_m_n_s16, vmlaq_m_n_u8, vmlaq_m_n_u32, vmlaq_m_n_u16, vmlasq_m_n_s8, vmlasq_m_n_s32, vmlasq_m_n_s16, vmlasq_m_n_u8, vmlasq_m_n_u32, vmlasq_m_n_u16, vmlsdavaq_p_s8, vmlsdavaq_p_s32, vmlsdavaq_p_s16, vmlsdavaxq_p_s8, vmlsdavaxq_p_s32, vmlsdavaxq_p_s16, vmulhq_m_s8, vmulhq_m_s32, vmulhq_m_s16, vmulhq_m_u8, vmulhq_m_u32, vmulhq_m_u16, vmullbq_int_m_s8, vmullbq_int_m_s32, vmullbq_int_m_s16, vmullbq_int_m_u8, vmullbq_int_m_u32, vmullbq_int_m_u16, vmulltq_int_m_s8, vmulltq_int_m_s32, vmulltq_int_m_s16, vmulltq_int_m_u8, vmulltq_int_m_u32, vmulltq_int_m_u16, vmulq_m_n_s8, vmulq_m_n_s32, vmulq_m_n_s16, vmulq_m_n_u8, vmulq_m_n_u32, vmulq_m_n_u16, vmulq_m_s8, vmulq_m_s32, vmulq_m_s16, vmulq_m_u8, vmulq_m_u32, vmulq_m_u16, vornq_m_s8, vornq_m_s32, vornq_m_s16, vornq_m_u8, vornq_m_u32, vornq_m_u16, vorrq_m_s8, vorrq_m_s32, vorrq_m_s16, vorrq_m_u8, vorrq_m_u32, vorrq_m_u16, vqaddq_m_n_s8, vqaddq_m_n_s32, vqaddq_m_n_s16, vqaddq_m_n_u8, vqaddq_m_n_u32, vqaddq_m_n_u16, vqaddq_m_s8, vqaddq_m_s32, vqaddq_m_s16, vqaddq_m_u8, vqaddq_m_u32, vqaddq_m_u16, vqdmladhq_m_s8, vqdmladhq_m_s32, vqdmladhq_m_s16, vqdmladhxq_m_s8, vqdmladhxq_m_s32, vqdmladhxq_m_s16, vqdmlahq_m_n_s8, vqdmlahq_m_n_s32, vqdmlahq_m_n_s16, vqdmlahq_m_n_u8, vqdmlahq_m_n_u32, vqdmlahq_m_n_u16, vqdmlsdhq_m_s8, vqdmlsdhq_m_s32, vqdmlsdhq_m_s16, vqdmlsdhxq_m_s8, vqdmlsdhxq_m_s32, vqdmlsdhxq_m_s16, vqdmulhq_m_n_s8, vqdmulhq_m_n_s32, vqdmulhq_m_n_s16, vqdmulhq_m_s8, vqdmulhq_m_s32, vqdmulhq_m_s16, vqrdmladhq_m_s8, vqrdmladhq_m_s32, vqrdmladhq_m_s16, vqrdmladhxq_m_s8, vqrdmladhxq_m_s32, vqrdmladhxq_m_s16, vqrdmlahq_m_n_s8, vqrdmlahq_m_n_s32, vqrdmlahq_m_n_s16, vqrdmlahq_m_n_u8, vqrdmlahq_m_n_u32, vqrdmlahq_m_n_u16, vqrdmlashq_m_n_s8, vqrdmlashq_m_n_s32, vqrdmlashq_m_n_s16, vqrdmlashq_m_n_u8, vqrdmlashq_m_n_u32, vqrdmlashq_m_n_u16, vqrdmlsdhq_m_s8, vqrdmlsdhq_m_s32, vqrdmlsdhq_m_s16, vqrdmlsdhxq_m_s8, vqrdmlsdhxq_m_s32, vqrdmlsdhxq_m_s16, vqrdmulhq_m_n_s8, vqrdmulhq_m_n_s32, vqrdmulhq_m_n_s16, vqrdmulhq_m_s8, vqrdmulhq_m_s32, vqrdmulhq_m_s16, vqrshlq_m_s8, vqrshlq_m_s32, vqrshlq_m_s16, vqrshlq_m_u8, vqrshlq_m_u32, vqrshlq_m_u16, vqshlq_m_n_s8, vqshlq_m_n_s32, vqshlq_m_n_s16, vqshlq_m_n_u8, vqshlq_m_n_u32, vqshlq_m_n_u16, vqshlq_m_s8, vqshlq_m_s32, vqshlq_m_s16, vqshlq_m_u8, vqshlq_m_u32, vqshlq_m_u16, vqsubq_m_n_s8, vqsubq_m_n_s32, vqsubq_m_n_s16, vqsubq_m_n_u8, vqsubq_m_n_u32, vqsubq_m_n_u16, vqsubq_m_s8, vqsubq_m_s32, vqsubq_m_s16, vqsubq_m_u8, vqsubq_m_u32, vqsubq_m_u16, vrhaddq_m_s8, vrhaddq_m_s32, vrhaddq_m_s16, vrhaddq_m_u8, vrhaddq_m_u32, vrhaddq_m_u16, vrmulhq_m_s8, vrmulhq_m_s32, vrmulhq_m_s16, vrmulhq_m_u8, vrmulhq_m_u32, vrmulhq_m_u16, vrshlq_m_s8, vrshlq_m_s32, vrshlq_m_s16, vrshlq_m_u8, vrshlq_m_u32, vrshlq_m_u16, vrshrq_m_n_s8, vrshrq_m_n_s32, vrshrq_m_n_s16, vrshrq_m_n_u8, vrshrq_m_n_u32, vrshrq_m_n_u16, vshlq_m_n_s8, vshlq_m_n_s32, vshlq_m_n_s16, vshlq_m_n_u8, vshlq_m_n_u32, vshlq_m_n_u16, vshrq_m_n_s8, vshrq_m_n_s32, vshrq_m_n_s16, vshrq_m_n_u8, vshrq_m_n_u32, vshrq_m_n_u16, vsliq_m_n_s8, vsliq_m_n_s32, vsliq_m_n_s16, vsliq_m_n_u8, vsliq_m_n_u32, vsliq_m_n_u16, vsubq_m_n_s8, vsubq_m_n_s32, vsubq_m_n_s16, vsubq_m_n_u8, vsubq_m_n_u32, vsubq_m_n_u16.
Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details.
[1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics
2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
Mihail Ionescu <mihail.ionescu@arm.com>
Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* config/arm/arm_mve.h (vabdq_m_s8): Define macro.
(vabdq_m_s32): Likewise.
(vabdq_m_s16): Likewise.
(vabdq_m_u8): Likewise.
(vabdq_m_u32): Likewise.
(vabdq_m_u16): Likewise.
(vaddq_m_n_s8): Likewise.
(vaddq_m_n_s32): Likewise.
(vaddq_m_n_s16): Likewise.
(vaddq_m_n_u8): Likewise.
(vaddq_m_n_u32): Likewise.
(vaddq_m_n_u16): Likewise.
(vaddq_m_s8): Likewise.
(vaddq_m_s32): Likewise.
(vaddq_m_s16): Likewise.
(vaddq_m_u8): Likewise.
(vaddq_m_u32): Likewise.
(vaddq_m_u16): Likewise.
(vandq_m_s8): Likewise.
(vandq_m_s32): Likewise.
(vandq_m_s16): Likewise.
(vandq_m_u8): Likewise.
(vandq_m_u32): Likewise.
(vandq_m_u16): Likewise.
(vbicq_m_s8): Likewise.
(vbicq_m_s32): Likewise.
(vbicq_m_s16): Likewise.
(vbicq_m_u8): Likewise.
(vbicq_m_u32): Likewise.
(vbicq_m_u16): Likewise.
(vbrsrq_m_n_s8): Likewise.
(vbrsrq_m_n_s32): Likewise.
(vbrsrq_m_n_s16): Likewise.
(vbrsrq_m_n_u8): Likewise.
(vbrsrq_m_n_u32): Likewise.
(vbrsrq_m_n_u16): Likewise.
(vcaddq_rot270_m_s8): Likewise.
(vcaddq_rot270_m_s32): Likewise.
(vcaddq_rot270_m_s16): Likewise.
(vcaddq_rot270_m_u8): Likewise.
(vcaddq_rot270_m_u32): Likewise.
(vcaddq_rot270_m_u16): Likewise.
(vcaddq_rot90_m_s8): Likewise.
(vcaddq_rot90_m_s32): Likewise.
(vcaddq_rot90_m_s16): Likewise.
(vcaddq_rot90_m_u8): Likewise.
(vcaddq_rot90_m_u32): Likewise.
(vcaddq_rot90_m_u16): Likewise.
(veorq_m_s8): Likewise.
(veorq_m_s32): Likewise.
(veorq_m_s16): Likewise.
(veorq_m_u8): Likewise.
(veorq_m_u32): Likewise.
(veorq_m_u16): Likewise.
(vhaddq_m_n_s8): Likewise.
(vhaddq_m_n_s32): Likewise.
(vhaddq_m_n_s16): Likewise.
(vhaddq_m_n_u8): Likewise.
(vhaddq_m_n_u32): Likewise.
(vhaddq_m_n_u16): Likewise.
(vhaddq_m_s8): Likewise.
(vhaddq_m_s32): Likewise.
(vhaddq_m_s16): Likewise.
(vhaddq_m_u8): Likewise.
(vhaddq_m_u32): Likewise.
(vhaddq_m_u16): Likewise.
(vhcaddq_rot270_m_s8): Likewise.
(vhcaddq_rot270_m_s32): Likewise.
(vhcaddq_rot270_m_s16): Likewise.
(vhcaddq_rot90_m_s8): Likewise.
(vhcaddq_rot90_m_s32): Likewise.
(vhcaddq_rot90_m_s16): Likewise.
(vhsubq_m_n_s8): Likewise.
(vhsubq_m_n_s32): Likewise.
(vhsubq_m_n_s16): Likewise.
(vhsubq_m_n_u8): Likewise.
(vhsubq_m_n_u32): Likewise.
(vhsubq_m_n_u16): Likewise.
(vhsubq_m_s8): Likewise.
(vhsubq_m_s32): Likewise.
(vhsubq_m_s16): Likewise.
(vhsubq_m_u8): Likewise.
(vhsubq_m_u32): Likewise.
(vhsubq_m_u16): Likewise.
(vmaxq_m_s8): Likewise.
(vmaxq_m_s32): Likewise.
(vmaxq_m_s16): Likewise.
(vmaxq_m_u8): Likewise.
(vmaxq_m_u32): Likewise.
(vmaxq_m_u16): Likewise.
(vminq_m_s8): Likewise.
(vminq_m_s32): Likewise.
(vminq_m_s16): Likewise.
(vminq_m_u8): Likewise.
(vminq_m_u32): Likewise.
(vminq_m_u16): Likewise.
(vmladavaq_p_s8): Likewise.
(vmladavaq_p_s32): Likewise.
(vmladavaq_p_s16): Likewise.
(vmladavaq_p_u8): Likewise.
(vmladavaq_p_u32): Likewise.
(vmladavaq_p_u16): Likewise.
(vmladavaxq_p_s8): Likewise.
(vmladavaxq_p_s32): Likewise.
(vmladavaxq_p_s16): Likewise.
(vmlaq_m_n_s8): Likewise.
(vmlaq_m_n_s32): Likewise.
(vmlaq_m_n_s16): Likewise.
(vmlaq_m_n_u8): Likewise.
(vmlaq_m_n_u32): Likewise.
(vmlaq_m_n_u16): Likewise.
(vmlasq_m_n_s8): Likewise.
(vmlasq_m_n_s32): Likewise.
(vmlasq_m_n_s16): Likewise.
(vmlasq_m_n_u8): Likewise.
(vmlasq_m_n_u32): Likewise.
(vmlasq_m_n_u16): Likewise.
(vmlsdavaq_p_s8): Likewise.
(vmlsdavaq_p_s32): Likewise.
(vmlsdavaq_p_s16): Likewise.
(vmlsdavaxq_p_s8): Likewise.
(vmlsdavaxq_p_s32): Likewise.
(vmlsdavaxq_p_s16): Likewise.
(vmulhq_m_s8): Likewise.
(vmulhq_m_s32): Likewise.
(vmulhq_m_s16): Likewise.
(vmulhq_m_u8): Likewise.
(vmulhq_m_u32): Likewise.
(vmulhq_m_u16): Likewise.
(vmullbq_int_m_s8): Likewise.
(vmullbq_int_m_s32): Likewise.
(vmullbq_int_m_s16): Likewise.
(vmullbq_int_m_u8): Likewise.
(vmullbq_int_m_u32): Likewise.
(vmullbq_int_m_u16): Likewise.
(vmulltq_int_m_s8): Likewise.
(vmulltq_int_m_s32): Likewise.
(vmulltq_int_m_s16): Likewise.
(vmulltq_int_m_u8): Likewise.
(vmulltq_int_m_u32): Likewise.
(vmulltq_int_m_u16): Likewise.
(vmulq_m_n_s8): Likewise.
(vmulq_m_n_s32): Likewise.
(vmulq_m_n_s16): Likewise.
(vmulq_m_n_u8): Likewise.
(vmulq_m_n_u32): Likewise.
(vmulq_m_n_u16): Likewise.
(vmulq_m_s8): Likewise.
(vmulq_m_s32): Likewise.
(vmulq_m_s16): Likewise.
(vmulq_m_u8): Likewise.
(vmulq_m_u32): Likewise.
(vmulq_m_u16): Likewise.
(vornq_m_s8): Likewise.
(vornq_m_s32): Likewise.
(vornq_m_s16): Likewise.
(vornq_m_u8): Likewise.
(vornq_m_u32): Likewise.
(vornq_m_u16): Likewise.
(vorrq_m_s8): Likewise.
(vorrq_m_s32): Likewise.
(vorrq_m_s16): Likewise.
(vorrq_m_u8): Likewise.
(vorrq_m_u32): Likewise.
(vorrq_m_u16): Likewise.
(vqaddq_m_n_s8): Likewise.
(vqaddq_m_n_s32): Likewise.
(vqaddq_m_n_s16): Likewise.
(vqaddq_m_n_u8): Likewise.
(vqaddq_m_n_u32): Likewise.
(vqaddq_m_n_u16): Likewise.
(vqaddq_m_s8): Likewise.
(vqaddq_m_s32): Likewise.
(vqaddq_m_s16): Likewise.
(vqaddq_m_u8): Likewise.
(vqaddq_m_u32): Likewise.
(vqaddq_m_u16): Likewise.
(vqdmladhq_m_s8): Likewise.
(vqdmladhq_m_s32): Likewise.
(vqdmladhq_m_s16): Likewise.
(vqdmladhxq_m_s8): Likewise.
(vqdmladhxq_m_s32): Likewise.
(vqdmladhxq_m_s16): Likewise.
(vqdmlahq_m_n_s8): Likewise.
(vqdmlahq_m_n_s32): Likewise.
(vqdmlahq_m_n_s16): Likewise.
(vqdmlahq_m_n_u8): Likewise.
(vqdmlahq_m_n_u32): Likewise.
(vqdmlahq_m_n_u16): Likewise.
(vqdmlsdhq_m_s8): Likewise.
(vqdmlsdhq_m_s32): Likewise.
(vqdmlsdhq_m_s16): Likewise.
(vqdmlsdhxq_m_s8): Likewise.
(vqdmlsdhxq_m_s32): Likewise.
(vqdmlsdhxq_m_s16): Likewise.
(vqdmulhq_m_n_s8): Likewise.
(vqdmulhq_m_n_s32): Likewise.
(vqdmulhq_m_n_s16): Likewise.
(vqdmulhq_m_s8): Likewise.
(vqdmulhq_m_s32): Likewise.
(vqdmulhq_m_s16): Likewise.
(vqrdmladhq_m_s8): Likewise.
(vqrdmladhq_m_s32): Likewise.
(vqrdmladhq_m_s16): Likewise.
(vqrdmladhxq_m_s8): Likewise.
(vqrdmladhxq_m_s32): Likewise.
(vqrdmladhxq_m_s16): Likewise.
(vqrdmlahq_m_n_s8): Likewise.
(vqrdmlahq_m_n_s32): Likewise.
(vqrdmlahq_m_n_s16): Likewise.
(vqrdmlahq_m_n_u8): Likewise.
(vqrdmlahq_m_n_u32): Likewise.
(vqrdmlahq_m_n_u16): Likewise.
(vqrdmlashq_m_n_s8): Likewise.
(vqrdmlashq_m_n_s32): Likewise.
(vqrdmlashq_m_n_s16): Likewise.
(vqrdmlashq_m_n_u8): Likewise.
(vqrdmlashq_m_n_u32): Likewise.
(vqrdmlashq_m_n_u16): Likewise.
(vqrdmlsdhq_m_s8): Likewise.
(vqrdmlsdhq_m_s32): Likewise.
(vqrdmlsdhq_m_s16): Likewise.
(vqrdmlsdhxq_m_s8): Likewise.
(vqrdmlsdhxq_m_s32): Likewise.
(vqrdmlsdhxq_m_s16): Likewise.
(vqrdmulhq_m_n_s8): Likewise.
(vqrdmulhq_m_n_s32): Likewise.
(vqrdmulhq_m_n_s16): Likewise.
(vqrdmulhq_m_s8): Likewise.
(vqrdmulhq_m_s32): Likewise.
(vqrdmulhq_m_s16): Likewise.
(vqrshlq_m_s8): Likewise.
(vqrshlq_m_s32): Likewise.
(vqrshlq_m_s16): Likewise.
(vqrshlq_m_u8): Likewise.
(vqrshlq_m_u32): Likewise.
(vqrshlq_m_u16): Likewise.
(vqshlq_m_n_s8): Likewise.
(vqshlq_m_n_s32): Likewise.
(vqshlq_m_n_s16): Likewise.
(vqshlq_m_n_u8): Likewise.
(vqshlq_m_n_u32): Likewise.
(vqshlq_m_n_u16): Likewise.
(vqshlq_m_s8): Likewise.
(vqshlq_m_s32): Likewise.
(vqshlq_m_s16): Likewise.
(vqshlq_m_u8): Likewise.
(vqshlq_m_u32): Likewise.
(vqshlq_m_u16): Likewise.
(vqsubq_m_n_s8): Likewise.
(vqsubq_m_n_s32): Likewise.
(vqsubq_m_n_s16): Likewise.
(vqsubq_m_n_u8): Likewise.
(vqsubq_m_n_u32): Likewise.
(vqsubq_m_n_u16): Likewise.
(vqsubq_m_s8): Likewise.
(vqsubq_m_s32): Likewise.
(vqsubq_m_s16): Likewise.
(vqsubq_m_u8): Likewise.
(vqsubq_m_u32): Likewise.
(vqsubq_m_u16): Likewise.
(vrhaddq_m_s8): Likewise.
(vrhaddq_m_s32): Likewise.
(vrhaddq_m_s16): Likewise.
(vrhaddq_m_u8): Likewise.
(vrhaddq_m_u32): Likewise.
(vrhaddq_m_u16): Likewise.
(vrmulhq_m_s8): Likewise.
(vrmulhq_m_s32): Likewise.
(vrmulhq_m_s16): Likewise.
(vrmulhq_m_u8): Likewise.
(vrmulhq_m_u32): Likewise.
(vrmulhq_m_u16): Likewise.
(vrshlq_m_s8): Likewise.
(vrshlq_m_s32): Likewise.
(vrshlq_m_s16): Likewise.
(vrshlq_m_u8): Likewise.
(vrshlq_m_u32): Likewise.
(vrshlq_m_u16): Likewise.
(vrshrq_m_n_s8): Likewise.
(vrshrq_m_n_s32): Likewise.
(vrshrq_m_n_s16): Likewise.
(vrshrq_m_n_u8): Likewise.
(vrshrq_m_n_u32): Likewise.
(vrshrq_m_n_u16): Likewise.
(vshlq_m_n_s8): Likewise.
(vshlq_m_n_s32): Likewise.
(vshlq_m_n_s16): Likewise.
(vshlq_m_n_u8): Likewise.
(vshlq_m_n_u32): Likewise.
(vshlq_m_n_u16): Likewise.
(vshrq_m_n_s8): Likewise.
(vshrq_m_n_s32): Likewise.
(vshrq_m_n_s16): Likewise.
(vshrq_m_n_u8): Likewise.
(vshrq_m_n_u32): Likewise.
(vshrq_m_n_u16): Likewise.
(vsliq_m_n_s8): Likewise.
(vsliq_m_n_s32): Likewise.
(vsliq_m_n_s16): Likewise.
(vsliq_m_n_u8): Likewise.
(vsliq_m_n_u32): Likewise.
(vsliq_m_n_u16): Likewise.
(vsubq_m_n_s8): Likewise.
(vsubq_m_n_s32): Likewise.
(vsubq_m_n_s16): Likewise.
(vsubq_m_n_u8): Likewise.
(vsubq_m_n_u32): Likewise.
(vsubq_m_n_u16): Likewise.
(__arm_vabdq_m_s8): Define intrinsic.
(__arm_vabdq_m_s32): Likewise.
(__arm_vabdq_m_s16): Likewise.
(__arm_vabdq_m_u8): Likewise.
(__arm_vabdq_m_u32): Likewise.
(__arm_vabdq_m_u16): Likewise.
(__arm_vaddq_m_n_s8): Likewise.
(__arm_vaddq_m_n_s32): Likewise.
(__arm_vaddq_m_n_s16): Likewise.
(__arm_vaddq_m_n_u8): Likewise.
(__arm_vaddq_m_n_u32): Likewise.
(__arm_vaddq_m_n_u16): Likewise.
(__arm_vaddq_m_s8): Likewise.
(__arm_vaddq_m_s32): Likewise.
(__arm_vaddq_m_s16): Likewise.
(__arm_vaddq_m_u8): Likewise.
(__arm_vaddq_m_u32): Likewise.
(__arm_vaddq_m_u16): Likewise.
(__arm_vandq_m_s8): Likewise.
(__arm_vandq_m_s32): Likewise.
(__arm_vandq_m_s16): Likewise.
(__arm_vandq_m_u8): Likewise.
(__arm_vandq_m_u32): Likewise.
(__arm_vandq_m_u16): Likewise.
(__arm_vbicq_m_s8): Likewise.
(__arm_vbicq_m_s32): Likewise.
(__arm_vbicq_m_s16): Likewise.
(__arm_vbicq_m_u8): Likewise.
(__arm_vbicq_m_u32): Likewise.
(__arm_vbicq_m_u16): Likewise.
(__arm_vbrsrq_m_n_s8): Likewise.
(__arm_vbrsrq_m_n_s32): Likewise.
(__arm_vbrsrq_m_n_s16): Likewise.
(__arm_vbrsrq_m_n_u8): Likewise.
(__arm_vbrsrq_m_n_u32): Likewise.
(__arm_vbrsrq_m_n_u16): Likewise.
(__arm_vcaddq_rot270_m_s8): Likewise.
(__arm_vcaddq_rot270_m_s32): Likewise.
(__arm_vcaddq_rot270_m_s16): Likewise.
(__arm_vcaddq_rot270_m_u8): Likewise.
(__arm_vcaddq_rot270_m_u32): Likewise.
(__arm_vcaddq_rot270_m_u16): Likewise.
(__arm_vcaddq_rot90_m_s8): Likewise.
(__arm_vcaddq_rot90_m_s32): Likewise.
(__arm_vcaddq_rot90_m_s16): Likewise.
(__arm_vcaddq_rot90_m_u8): Likewise.
(__arm_vcaddq_rot90_m_u32): Likewise.
(__arm_vcaddq_rot90_m_u16): Likewise.
(__arm_veorq_m_s8): Likewise.
(__arm_veorq_m_s32): Likewise.
(__arm_veorq_m_s16): Likewise.
(__arm_veorq_m_u8): Likewise.
(__arm_veorq_m_u32): Likewise.
(__arm_veorq_m_u16): Likewise.
(__arm_vhaddq_m_n_s8): Likewise.
(__arm_vhaddq_m_n_s32): Likewise.
(__arm_vhaddq_m_n_s16): Likewise.
(__arm_vhaddq_m_n_u8): Likewise.
(__arm_vhaddq_m_n_u32): Likewise.
(__arm_vhaddq_m_n_u16): Likewise.
(__arm_vhaddq_m_s8): Likewise.
(__arm_vhaddq_m_s32): Likewise.
(__arm_vhaddq_m_s16): Likewise.
(__arm_vhaddq_m_u8): Likewise.
(__arm_vhaddq_m_u32): Likewise.
(__arm_vhaddq_m_u16): Likewise.
(__arm_vhcaddq_rot270_m_s8): Likewise.
(__arm_vhcaddq_rot270_m_s32): Likewise.
(__arm_vhcaddq_rot270_m_s16): Likewise.
(__arm_vhcaddq_rot90_m_s8): Likewise.
(__arm_vhcaddq_rot90_m_s32): Likewise.
(__arm_vhcaddq_rot90_m_s16): Likewise.
(__arm_vhsubq_m_n_s8): Likewise.
(__arm_vhsubq_m_n_s32): Likewise.
(__arm_vhsubq_m_n_s16): Likewise.
(__arm_vhsubq_m_n_u8): Likewise.
(__arm_vhsubq_m_n_u32): Likewise.
(__arm_vhsubq_m_n_u16): Likewise.
(__arm_vhsubq_m_s8): Likewise.
(__arm_vhsubq_m_s32): Likewise.
(__arm_vhsubq_m_s16): Likewise.
(__arm_vhsubq_m_u8): Likewise.
(__arm_vhsubq_m_u32): Likewise.
(__arm_vhsubq_m_u16): Likewise.
(__arm_vmaxq_m_s8): Likewise.
(__arm_vmaxq_m_s32): Likewise.
(__arm_vmaxq_m_s16): Likewise.
(__arm_vmaxq_m_u8): Likewise.
(__arm_vmaxq_m_u32): Likewise.
(__arm_vmaxq_m_u16): Likewise.
(__arm_vminq_m_s8): Likewise.
(__arm_vminq_m_s32): Likewise.
(__arm_vminq_m_s16): Likewise.
(__arm_vminq_m_u8): Likewise.
(__arm_vminq_m_u32): Likewise.
(__arm_vminq_m_u16): Likewise.
(__arm_vmladavaq_p_s8): Likewise.
(__arm_vmladavaq_p_s32): Likewise.
(__arm_vmladavaq_p_s16): Likewise.
(__arm_vmladavaq_p_u8): Likewise.
(__arm_vmladavaq_p_u32): Likewise.
(__arm_vmladavaq_p_u16): Likewise.
(__arm_vmladavaxq_p_s8): Likewise.
(__arm_vmladavaxq_p_s32): Likewise.
(__arm_vmladavaxq_p_s16): Likewise.
(__arm_vmlaq_m_n_s8): Likewise.
(__arm_vmlaq_m_n_s32): Likewise.
(__arm_vmlaq_m_n_s16): Likewise.
(__arm_vmlaq_m_n_u8): Likewise.
(__arm_vmlaq_m_n_u32): Likewise.
(__arm_vmlaq_m_n_u16): Likewise.
(__arm_vmlasq_m_n_s8): Likewise.
(__arm_vmlasq_m_n_s32): Likewise.
(__arm_vmlasq_m_n_s16): Likewise.
(__arm_vmlasq_m_n_u8): Likewise.
(__arm_vmlasq_m_n_u32): Likewise.
(__arm_vmlasq_m_n_u16): Likewise.
(__arm_vmlsdavaq_p_s8): Likewise.
(__arm_vmlsdavaq_p_s32): Likewise.
(__arm_vmlsdavaq_p_s16): Likewise.
(__arm_vmlsdavaxq_p_s8): Likewise.
(__arm_vmlsdavaxq_p_s32): Likewise.
(__arm_vmlsdavaxq_p_s16): Likewise.
(__arm_vmulhq_m_s8): Likewise.
(__arm_vmulhq_m_s32): Likewise.
(__arm_vmulhq_m_s16): Likewise.
(__arm_vmulhq_m_u8): Likewise.
(__arm_vmulhq_m_u32): Likewise.
(__arm_vmulhq_m_u16): Likewise.
(__arm_vmullbq_int_m_s8): Likewise.
(__arm_vmullbq_int_m_s32): Likewise.
(__arm_vmullbq_int_m_s16): Likewise.
(__arm_vmullbq_int_m_u8): Likewise.
(__arm_vmullbq_int_m_u32): Likewise.
(__arm_vmullbq_int_m_u16): Likewise.
(__arm_vmulltq_int_m_s8): Likewise.
(__arm_vmulltq_int_m_s32): Likewise.
(__arm_vmulltq_int_m_s16): Likewise.
(__arm_vmulltq_int_m_u8): Likewise.
(__arm_vmulltq_int_m_u32): Likewise.
(__arm_vmulltq_int_m_u16): Likewise.
(__arm_vmulq_m_n_s8): Likewise.
(__arm_vmulq_m_n_s32): Likewise.
(__arm_vmulq_m_n_s16): Likewise.
(__arm_vmulq_m_n_u8): Likewise.
(__arm_vmulq_m_n_u32): Likewise.
(__arm_vmulq_m_n_u16): Likewise.
(__arm_vmulq_m_s8): Likewise.
(__arm_vmulq_m_s32): Likewise.
(__arm_vmulq_m_s16): Likewise.
(__arm_vmulq_m_u8): Likewise.
(__arm_vmulq_m_u32): Likewise.
(__arm_vmulq_m_u16): Likewise.
(__arm_vornq_m_s8): Likewise.
(__arm_vornq_m_s32): Likewise.
(__arm_vornq_m_s16): Likewise.
(__arm_vornq_m_u8): Likewise.
(__arm_vornq_m_u32): Likewise.
(__arm_vornq_m_u16): Likewise.
(__arm_vorrq_m_s8): Likewise.
(__arm_vorrq_m_s32): Likewise.
(__arm_vorrq_m_s16): Likewise.
(__arm_vorrq_m_u8): Likewise.
(__arm_vorrq_m_u32): Likewise.
(__arm_vorrq_m_u16): Likewise.
(__arm_vqaddq_m_n_s8): Likewise.
(__arm_vqaddq_m_n_s32): Likewise.
(__arm_vqaddq_m_n_s16): Likewise.
(__arm_vqaddq_m_n_u8): Likewise.
(__arm_vqaddq_m_n_u32): Likewise.
(__arm_vqaddq_m_n_u16): Likewise.
(__arm_vqaddq_m_s8): Likewise.
(__arm_vqaddq_m_s32): Likewise.
(__arm_vqaddq_m_s16): Likewise.
(__arm_vqaddq_m_u8): Likewise.
(__arm_vqaddq_m_u32): Likewise.
(__arm_vqaddq_m_u16): Likewise.
(__arm_vqdmladhq_m_s8): Likewise.
(__arm_vqdmladhq_m_s32): Likewise.
(__arm_vqdmladhq_m_s16): Likewise.
(__arm_vqdmladhxq_m_s8): Likewise.
(__arm_vqdmladhxq_m_s32): Likewise.
(__arm_vqdmladhxq_m_s16): Likewise.
(__arm_vqdmlahq_m_n_s8): Likewise.
(__arm_vqdmlahq_m_n_s32): Likewise.
(__arm_vqdmlahq_m_n_s16): Likewise.
(__arm_vqdmlahq_m_n_u8): Likewise.
(__arm_vqdmlahq_m_n_u32): Likewise.
(__arm_vqdmlahq_m_n_u16): Likewise.
(__arm_vqdmlsdhq_m_s8): Likewise.
(__arm_vqdmlsdhq_m_s32): Likewise.
(__arm_vqdmlsdhq_m_s16): Likewise.
(__arm_vqdmlsdhxq_m_s8): Likewise.
(__arm_vqdmlsdhxq_m_s32): Likewise.
(__arm_vqdmlsdhxq_m_s16): Likewise.
(__arm_vqdmulhq_m_n_s8): Likewise.
(__arm_vqdmulhq_m_n_s32): Likewise.
(__arm_vqdmulhq_m_n_s16): Likewise.
(__arm_vqdmulhq_m_s8): Likewise.
(__arm_vqdmulhq_m_s32): Likewise.
(__arm_vqdmulhq_m_s16): Likewise.
(__arm_vqrdmladhq_m_s8): Likewise.
(__arm_vqrdmladhq_m_s32): Likewise.
(__arm_vqrdmladhq_m_s16): Likewise.
(__arm_vqrdmladhxq_m_s8): Likewise.
(__arm_vqrdmladhxq_m_s32): Likewise.
(__arm_vqrdmladhxq_m_s16): Likewise.
(__arm_vqrdmlahq_m_n_s8): Likewise.
(__arm_vqrdmlahq_m_n_s32): Likewise.
(__arm_vqrdmlahq_m_n_s16): Likewise.
(__arm_vqrdmlahq_m_n_u8): Likewise.
(__arm_vqrdmlahq_m_n_u32): Likewise.
(__arm_vqrdmlahq_m_n_u16): Likewise.
(__arm_vqrdmlashq_m_n_s8): Likewise.
(__arm_vqrdmlashq_m_n_s32): Likewise.
(__arm_vqrdmlashq_m_n_s16): Likewise.
(__arm_vqrdmlashq_m_n_u8): Likewise.
(__arm_vqrdmlashq_m_n_u32): Likewise.
(__arm_vqrdmlashq_m_n_u16): Likewise.
(__arm_vqrdmlsdhq_m_s8): Likewise.
(__arm_vqrdmlsdhq_m_s32): Likewise.
(__arm_vqrdmlsdhq_m_s16): Likewise.
(__arm_vqrdmlsdhxq_m_s8): Likewise.
(__arm_vqrdmlsdhxq_m_s32): Likewise.
(__arm_vqrdmlsdhxq_m_s16): Likewise.
(__arm_vqrdmulhq_m_n_s8): Likewise.
(__arm_vqrdmulhq_m_n_s32): Likewise.
(__arm_vqrdmulhq_m_n_s16): Likewise.
(__arm_vqrdmulhq_m_s8): Likewise.
(__arm_vqrdmulhq_m_s32): Likewise.
(__arm_vqrdmulhq_m_s16): Likewise.
(__arm_vqrshlq_m_s8): Likewise.
(__arm_vqrshlq_m_s32): Likewise.
(__arm_vqrshlq_m_s16): Likewise.
(__arm_vqrshlq_m_u8): Likewise.
(__arm_vqrshlq_m_u32): Likewise.
(__arm_vqrshlq_m_u16): Likewise.
(__arm_vqshlq_m_n_s8): Likewise.
(__arm_vqshlq_m_n_s32): Likewise.
(__arm_vqshlq_m_n_s16): Likewise.
(__arm_vqshlq_m_n_u8): Likewise.
(__arm_vqshlq_m_n_u32): Likewise.
(__arm_vqshlq_m_n_u16): Likewise.
(__arm_vqshlq_m_s8): Likewise.
(__arm_vqshlq_m_s32): Likewise.
(__arm_vqshlq_m_s16): Likewise.
(__arm_vqshlq_m_u8): Likewise.
(__arm_vqshlq_m_u32): Likewise.
(__arm_vqshlq_m_u16): Likewise.
(__arm_vqsubq_m_n_s8): Likewise.
(__arm_vqsubq_m_n_s32): Likewise.
(__arm_vqsubq_m_n_s16): Likewise.
(__arm_vqsubq_m_n_u8): Likewise.
(__arm_vqsubq_m_n_u32): Likewise.
(__arm_vqsubq_m_n_u16): Likewise.
(__arm_vqsubq_m_s8): Likewise.
(__arm_vqsubq_m_s32): Likewise.
(__arm_vqsubq_m_s16): Likewise.
(__arm_vqsubq_m_u8): Likewise.
(__arm_vqsubq_m_u32): Likewise.
(__arm_vqsubq_m_u16): Likewise.
(__arm_vrhaddq_m_s8): Likewise.
(__arm_vrhaddq_m_s32): Likewise.
(__arm_vrhaddq_m_s16): Likewise.
(__arm_vrhaddq_m_u8): Likewise.
(__arm_vrhaddq_m_u32): Likewise.
(__arm_vrhaddq_m_u16): Likewise.
(__arm_vrmulhq_m_s8): Likewise.
(__arm_vrmulhq_m_s32): Likewise.
(__arm_vrmulhq_m_s16): Likewise.
(__arm_vrmulhq_m_u8): Likewise.
(__arm_vrmulhq_m_u32): Likewise.
(__arm_vrmulhq_m_u16): Likewise.
(__arm_vrshlq_m_s8): Likewise.
(__arm_vrshlq_m_s32): Likewise.
(__arm_vrshlq_m_s16): Likewise.
(__arm_vrshlq_m_u8): Likewise.
(__arm_vrshlq_m_u32): Likewise.
(__arm_vrshlq_m_u16): Likewise.
(__arm_vrshrq_m_n_s8): Likewise.
(__arm_vrshrq_m_n_s32): Likewise.
(__arm_vrshrq_m_n_s16): Likewise.
(__arm_vrshrq_m_n_u8): Likewise.
(__arm_vrshrq_m_n_u32): Likewise.
(__arm_vrshrq_m_n_u16): Likewise.
(__arm_vshlq_m_n_s8): Likewise.
(__arm_vshlq_m_n_s32): Likewise.
(__arm_vshlq_m_n_s16): Likewise.
(__arm_vshlq_m_n_u8): Likewise.
(__arm_vshlq_m_n_u32): Likewise.
(__arm_vshlq_m_n_u16): Likewise.
(__arm_vshrq_m_n_s8): Likewise.
(__arm_vshrq_m_n_s32): Likewise.
(__arm_vshrq_m_n_s16): Likewise.
(__arm_vshrq_m_n_u8): Likewise.
(__arm_vshrq_m_n_u32): Likewise.
(__arm_vshrq_m_n_u16): Likewise.
(__arm_vsliq_m_n_s8): Likewise.
(__arm_vsliq_m_n_s32): Likewise.
(__arm_vsliq_m_n_s16): Likewise.
(__arm_vsliq_m_n_u8): Likewise.
(__arm_vsliq_m_n_u32): Likewise.
(__arm_vsliq_m_n_u16): Likewise.
(__arm_vsubq_m_n_s8): Likewise.
(__arm_vsubq_m_n_s32): Likewise.
(__arm_vsubq_m_n_s16): Likewise.
(__arm_vsubq_m_n_u8): Likewise.
(__arm_vsubq_m_n_u32): Likewise.
(__arm_vsubq_m_n_u16): Likewise.
(vqdmladhq_m): Define polymorphic variant.
(vqdmladhxq_m): Likewise.
(vqdmlsdhq_m): Likewise.
(vqdmlsdhxq_m): Likewise.
(vabdq_m): Likewise.
(vandq_m): Likewise.
(vbicq_m): Likewise.
(vbrsrq_m_n): Likewise.
(vcaddq_rot270_m): Likewise.
(vcaddq_rot90_m): Likewise.
(veorq_m): Likewise.
(vmaxq_m): Likewise.
(vminq_m): Likewise.
(vmladavaq_p): Likewise.
(vmlaq_m_n): Likewise.
(vmlasq_m_n): Likewise.
(vmulhq_m): Likewise.
(vmullbq_int_m): Likewise.
(vmulltq_int_m): Likewise.
(vornq_m): Likewise.
(vorrq_m): Likewise.
(vqdmlahq_m_n): Likewise.
(vqrdmlahq_m_n): Likewise.
(vqrdmlashq_m_n): Likewise.
(vqrshlq_m): Likewise.
(vqshlq_m_n): Likewise.
(vqshlq_m): Likewise.
(vrhaddq_m): Likewise.
(vrmulhq_m): Likewise.
(vrshlq_m): Likewise.
(vrshrq_m_n): Likewise.
(vshlq_m_n): Likewise.
(vshrq_m_n): Likewise.
(vsliq_m): Likewise.
(vaddq_m_n): Likewise.
(vaddq_m): Likewise.
(vhaddq_m_n): Likewise.
(vhaddq_m): Likewise.
(vhcaddq_rot270_m): Likewise.
(vhcaddq_rot90_m): Likewise.
(vhsubq_m): Likewise.
(vhsubq_m_n): Likewise.
(vmulq_m_n): Likewise.
(vmulq_m): Likewise.
(vqaddq_m_n): Likewise.
(vqaddq_m): Likewise.
(vqdmulhq_m_n): Likewise.
(vqdmulhq_m): Likewise.
(vsubq_m_n): Likewise.
(vsliq_m_n): Likewise.
(vqsubq_m_n): Likewise.
(vqsubq_m): Likewise.
(vqrdmulhq_m): Likewise.
(vqrdmulhq_m_n): Likewise.
(vqrdmlsdhxq_m): Likewise.
(vqrdmlsdhq_m): Likewise.
(vqrdmladhq_m): Likewise.
(vqrdmladhxq_m): Likewise.
(vmlsdavaxq_p): Likewise.
(vmlsdavaq_p): Likewise.
(vmladavaxq_p): Likewise.
* config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_NONE_IMM_UNONE): Use
builtin qualifier.
(QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise.
(QUADOP_UNONE_UNONE_UNONE_IMM_UNONE): Likewise.
(QUADOP_UNONE_UNONE_UNONE_NONE_UNONE): Likewise.
(QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE): Likewise.
* config/arm/mve.md (VHSUBQ_M): Define iterators.
(VSLIQ_M_N): Likewise.
(VQRDMLAHQ_M_N): Likewise.
(VRSHLQ_M): Likewise.
(VMINQ_M): Likewise.
(VMULLBQ_INT_M): Likewise.
(VMULHQ_M): Likewise.
(VMULQ_M): Likewise.
(VHSUBQ_M_N): Likewise.
(VHADDQ_M_N): Likewise.
(VORRQ_M): Likewise.
(VRMULHQ_M): Likewise.
(VQADDQ_M): Likewise.
(VRSHRQ_M_N): Likewise.
(VQSUBQ_M_N): Likewise.
(VADDQ_M): Likewise.
(VORNQ_M): Likewise.
(VQDMLAHQ_M_N): Likewise.
(VRHADDQ_M): Likewise.
(VQSHLQ_M): Likewise.
(VANDQ_M): Likewise.
(VBICQ_M): Likewise.
(VSHLQ_M_N): Likewise.
(VCADDQ_ROT270_M): Likewise.
(VQRSHLQ_M): Likewise.
(VQADDQ_M_N): Likewise.
(VADDQ_M_N): Likewise.
(VMAXQ_M): Likewise.
(VQSUBQ_M): Likewise.
(VMLASQ_M_N): Likewise.
(VMLADAVAQ_P): Likewise.
(VBRSRQ_M_N): Likewise.
(VMULQ_M_N): Likewise.
(VCADDQ_ROT90_M): Likewise.
(VMULLTQ_INT_M): Likewise.
(VEORQ_M): Likewise.
(VSHRQ_M_N): Likewise.
(VSUBQ_M_N): Likewise.
(VHADDQ_M): Likewise.
(VABDQ_M): Likewise.
(VQRDMLASHQ_M_N): Likewise.
(VMLAQ_M_N): Likewise.
(VQSHLQ_M_N): Likewise.
(mve_vabdq_m_<supf><mode>): Define RTL pattern.
(mve_vaddq_m_n_<supf><mode>): Likewise.
(mve_vaddq_m_<supf><mode>): Likewise.
(mve_vandq_m_<supf><mode>): Likewise.
(mve_vbicq_m_<supf><mode>): Likewise.
(mve_vbrsrq_m_n_<supf><mode>): Likewise.
(mve_vcaddq_rot270_m_<supf><mode>): Likewise.
(mve_vcaddq_rot90_m_<supf><mode>): Likewise.
(mve_veorq_m_<supf><mode>): Likewise.
(mve_vhaddq_m_n_<supf><mode>): Likewise.
(mve_vhaddq_m_<supf><mode>): Likewise.
(mve_vhsubq_m_n_<supf><mode>): Likewise.
(mve_vhsubq_m_<supf><mode>): Likewise.
(mve_vmaxq_m_<supf><mode>): Likewise.
(mve_vminq_m_<supf><mode>): Likewise.
(mve_vmladavaq_p_<supf><mode>): Likewise.
(mve_vmlaq_m_n_<supf><mode>): Likewise.
(mve_vmlasq_m_n_<supf><mode>): Likewise.
(mve_vmulhq_m_<supf><mode>): Likewise.
(mve_vmullbq_int_m_<supf><mode>): Likewise.
(mve_vmulltq_int_m_<supf><mode>): Likewise.
(mve_vmulq_m_n_<supf><mode>): Likewise.
(mve_vmulq_m_<supf><mode>): Likewise.
(mve_vornq_m_<supf><mode>): Likewise.
(mve_vorrq_m_<supf><mode>): Likewise.
(mve_vqaddq_m_n_<supf><mode>): Likewise.
(mve_vqaddq_m_<supf><mode>): Likewise.
(mve_vqdmlahq_m_n_<supf><mode>): Likewise.
(mve_vqrdmlahq_m_n_<supf><mode>): Likewise.
(mve_vqrdmlashq_m_n_<supf><mode>): Likewise.
(mve_vqrshlq_m_<supf><mode>): Likewise.
(mve_vqshlq_m_n_<supf><mode>): Likewise.
(mve_vqshlq_m_<supf><mode>): Likewise.
(mve_vqsubq_m_n_<supf><mode>): Likewise.
(mve_vqsubq_m_<supf><mode>): Likewise.
(mve_vrhaddq_m_<supf><mode>): Likewise.
(mve_vrmulhq_m_<supf><mode>): Likewise.
(mve_vrshlq_m_<supf><mode>): Likewise.
(mve_vrshrq_m_n_<supf><mode>): Likewise.
(mve_vshlq_m_n_<supf><mode>): Likewise.
(mve_vshrq_m_n_<supf><mode>): Likewise.
(mve_vsliq_m_n_<supf><mode>): Likewise.
(mve_vsubq_m_n_<supf><mode>): Likewise.
(mve_vhcaddq_rot270_m_s<mode>): Likewise.
(mve_vhcaddq_rot90_m_s<mode>): Likewise.
(mve_vmladavaxq_p_s<mode>): Likewise.
(mve_vmlsdavaq_p_s<mode>): Likewise.
(mve_vmlsdavaxq_p_s<mode>): Likewise.
(mve_vqdmladhq_m_s<mode>): Likewise.
(mve_vqdmladhxq_m_s<mode>): Likewise.
(mve_vqdmlsdhq_m_s<mode>): Likewise.
(mve_vqdmlsdhxq_m_s<mode>): Likewise.
(mve_vqdmulhq_m_n_s<mode>): Likewise.
(mve_vqdmulhq_m_s<mode>): Likewise.
(mve_vqrdmladhq_m_s<mode>): Likewise.
(mve_vqrdmladhxq_m_s<mode>): Likewise.
(mve_vqrdmlsdhq_m_s<mode>): Likewise.
(mve_vqrdmlsdhxq_m_s<mode>): Likewise.
(mve_vqrdmulhq_m_n_s<mode>): Likewise.
(mve_vqrdmulhq_m_s<mode>): Likewise.
gcc/testsuite/ChangeLog:
2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
Mihail Ionescu <mihail.ionescu@arm.com>
Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* gcc.target/arm/mve/intrinsics/vabdq_m_s16.c: New test.
* gcc.target/arm/mve/intrinsics/vabdq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabdq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabdq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabdq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabdq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhaddq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhaddq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhaddq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhaddq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhaddq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhaddq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhsubq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhsubq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhsubq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhsubq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhsubq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhsubq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavaq_p_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavaq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavaq_p_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavaq_p_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavaq_p_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavaxq_p_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavaxq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavaxq_p_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlasq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulhq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulhq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulhq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulhq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulhq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulhq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmullbq_int_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmullbq_int_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmullbq_int_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmullbq_int_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmullbq_int_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmullbq_int_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulltq_int_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulltq_int_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulltq_int_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulltq_int_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulltq_int_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulltq_int_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmladhq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmladhq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmladhq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmulhq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmulhq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmulhq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshlq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshlq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshlq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshlq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshlq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshlq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrhaddq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrhaddq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrhaddq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrhaddq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrhaddq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrhaddq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmulhq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmulhq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmulhq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmulhq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmulhq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmulhq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshlq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshlq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshlq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsliq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsliq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsliq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsliq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsliq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsliq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c: Likewise.
Diff:
---
gcc/ChangeLog | 793 ++++++
gcc/config/arm/arm_mve.h | 3012 ++++++++++++++++++++
gcc/config/arm/arm_mve_builtins.def | 100 +
gcc/config/arm/mve.md | 1125 +++++++-
gcc/testsuite/ChangeLog | 314 ++
.../gcc.target/arm/mve/intrinsics/vabdq_m_s16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vabdq_m_s32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vabdq_m_s8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vabdq_m_u16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vabdq_m_u32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vabdq_m_u8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vaddq_m_n_s16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vaddq_m_n_s32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vaddq_m_n_s8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vaddq_m_n_u16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vaddq_m_n_u32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vaddq_m_n_u8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vaddq_m_s16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vaddq_m_s32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vaddq_m_s8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vaddq_m_u16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vaddq_m_u32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vaddq_m_u8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vandq_m_s16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vandq_m_s32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vandq_m_s8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vandq_m_u16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vandq_m_u32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vandq_m_u8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vbicq_m_s16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vbicq_m_s32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vbicq_m_s8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vbicq_m_u16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vbicq_m_u32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vbicq_m_u8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c | 24 +
.../arm/mve/intrinsics/vcaddq_rot270_m_s16.c | 24 +
.../arm/mve/intrinsics/vcaddq_rot270_m_s32.c | 24 +
.../arm/mve/intrinsics/vcaddq_rot270_m_s8.c | 24 +
.../arm/mve/intrinsics/vcaddq_rot270_m_u16.c | 24 +
.../arm/mve/intrinsics/vcaddq_rot270_m_u32.c | 24 +
.../arm/mve/intrinsics/vcaddq_rot270_m_u8.c | 24 +
.../arm/mve/intrinsics/vcaddq_rot90_m_s16.c | 24 +
.../arm/mve/intrinsics/vcaddq_rot90_m_s32.c | 24 +
.../arm/mve/intrinsics/vcaddq_rot90_m_s8.c | 24 +
.../arm/mve/intrinsics/vcaddq_rot90_m_u16.c | 24 +
.../arm/mve/intrinsics/vcaddq_rot90_m_u32.c | 24 +
.../arm/mve/intrinsics/vcaddq_rot90_m_u8.c | 24 +
.../gcc.target/arm/mve/intrinsics/veorq_m_s16.c | 24 +
.../gcc.target/arm/mve/intrinsics/veorq_m_s32.c | 24 +
.../gcc.target/arm/mve/intrinsics/veorq_m_s8.c | 24 +
.../gcc.target/arm/mve/intrinsics/veorq_m_u16.c | 24 +
.../gcc.target/arm/mve/intrinsics/veorq_m_u32.c | 24 +
.../gcc.target/arm/mve/intrinsics/veorq_m_u8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vhaddq_m_s16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vhaddq_m_s32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vhaddq_m_s8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vhaddq_m_u16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vhaddq_m_u32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vhaddq_m_u8.c | 24 +
.../arm/mve/intrinsics/vhcaddq_rot270_m_s16.c | 24 +
.../arm/mve/intrinsics/vhcaddq_rot270_m_s32.c | 24 +
.../arm/mve/intrinsics/vhcaddq_rot270_m_s8.c | 24 +
.../arm/mve/intrinsics/vhcaddq_rot90_m_s16.c | 24 +
.../arm/mve/intrinsics/vhcaddq_rot90_m_s32.c | 24 +
.../arm/mve/intrinsics/vhcaddq_rot90_m_s8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vhsubq_m_s16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vhsubq_m_s32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vhsubq_m_s8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vhsubq_m_u16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vhsubq_m_u32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vhsubq_m_u8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vminq_m_s16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vminq_m_s32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vminq_m_s8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vminq_m_u16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vminq_m_u32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vminq_m_u8.c | 24 +
.../arm/mve/intrinsics/vmladavaq_p_s16.c | 23 +
.../arm/mve/intrinsics/vmladavaq_p_s32.c | 23 +
.../gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c | 23 +
.../arm/mve/intrinsics/vmladavaq_p_u16.c | 23 +
.../arm/mve/intrinsics/vmladavaq_p_u32.c | 23 +
.../gcc.target/arm/mve/intrinsics/vmladavaq_p_u8.c | 23 +
.../arm/mve/intrinsics/vmladavaxq_p_s16.c | 23 +
.../arm/mve/intrinsics/vmladavaxq_p_s32.c | 23 +
.../arm/mve/intrinsics/vmladavaxq_p_s8.c | 23 +
.../gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vmlasq_m_n_u32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c | 24 +
.../arm/mve/intrinsics/vmlsdavaq_p_s16.c | 23 +
.../arm/mve/intrinsics/vmlsdavaq_p_s32.c | 23 +
.../gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c | 23 +
.../arm/mve/intrinsics/vmlsdavaxq_p_s16.c | 23 +
.../arm/mve/intrinsics/vmlsdavaxq_p_s32.c | 23 +
.../arm/mve/intrinsics/vmlsdavaxq_p_s8.c | 23 +
.../gcc.target/arm/mve/intrinsics/vmulhq_m_s16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vmulhq_m_s32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vmulhq_m_s8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vmulhq_m_u16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vmulhq_m_u32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vmulhq_m_u8.c | 24 +
.../arm/mve/intrinsics/vmullbq_int_m_s16.c | 24 +
.../arm/mve/intrinsics/vmullbq_int_m_s32.c | 24 +
.../arm/mve/intrinsics/vmullbq_int_m_s8.c | 24 +
.../arm/mve/intrinsics/vmullbq_int_m_u16.c | 24 +
.../arm/mve/intrinsics/vmullbq_int_m_u32.c | 24 +
.../arm/mve/intrinsics/vmullbq_int_m_u8.c | 24 +
.../arm/mve/intrinsics/vmulltq_int_m_s16.c | 24 +
.../arm/mve/intrinsics/vmulltq_int_m_s32.c | 24 +
.../arm/mve/intrinsics/vmulltq_int_m_s8.c | 24 +
.../arm/mve/intrinsics/vmulltq_int_m_u16.c | 24 +
.../arm/mve/intrinsics/vmulltq_int_m_u32.c | 24 +
.../arm/mve/intrinsics/vmulltq_int_m_u8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vmulq_m_s16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vmulq_m_s32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vmulq_m_s8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vmulq_m_u16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vmulq_m_u32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vmulq_m_u8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vornq_m_s16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vornq_m_s32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vornq_m_s8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vornq_m_u16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vornq_m_u32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vornq_m_u8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vorrq_m_s16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vorrq_m_s32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vorrq_m_s8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vorrq_m_u16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vorrq_m_u32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vorrq_m_u8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c | 24 +
.../arm/mve/intrinsics/vqdmladhq_m_s16.c | 24 +
.../arm/mve/intrinsics/vqdmladhq_m_s32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vqdmladhq_m_s8.c | 24 +
.../arm/mve/intrinsics/vqdmladhxq_m_s16.c | 24 +
.../arm/mve/intrinsics/vqdmladhxq_m_s32.c | 24 +
.../arm/mve/intrinsics/vqdmladhxq_m_s8.c | 24 +
.../arm/mve/intrinsics/vqdmlahq_m_n_s16.c | 24 +
.../arm/mve/intrinsics/vqdmlahq_m_n_s32.c | 24 +
.../arm/mve/intrinsics/vqdmlahq_m_n_s8.c | 24 +
.../arm/mve/intrinsics/vqdmlsdhq_m_s16.c | 24 +
.../arm/mve/intrinsics/vqdmlsdhq_m_s32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s8.c | 24 +
.../arm/mve/intrinsics/vqdmlsdhxq_m_s16.c | 24 +
.../arm/mve/intrinsics/vqdmlsdhxq_m_s32.c | 24 +
.../arm/mve/intrinsics/vqdmlsdhxq_m_s8.c | 24 +
.../arm/mve/intrinsics/vqdmulhq_m_n_s16.c | 24 +
.../arm/mve/intrinsics/vqdmulhq_m_n_s32.c | 24 +
.../arm/mve/intrinsics/vqdmulhq_m_n_s8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vqdmulhq_m_s16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vqdmulhq_m_s32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vqdmulhq_m_s8.c | 24 +
.../arm/mve/intrinsics/vqrdmladhq_m_s16.c | 24 +
.../arm/mve/intrinsics/vqrdmladhq_m_s32.c | 24 +
.../arm/mve/intrinsics/vqrdmladhq_m_s8.c | 24 +
.../arm/mve/intrinsics/vqrdmladhxq_m_s16.c | 24 +
.../arm/mve/intrinsics/vqrdmladhxq_m_s32.c | 24 +
.../arm/mve/intrinsics/vqrdmladhxq_m_s8.c | 24 +
.../arm/mve/intrinsics/vqrdmlahq_m_n_s16.c | 24 +
.../arm/mve/intrinsics/vqrdmlahq_m_n_s32.c | 24 +
.../arm/mve/intrinsics/vqrdmlahq_m_n_s8.c | 24 +
.../arm/mve/intrinsics/vqrdmlashq_m_n_s16.c | 24 +
.../arm/mve/intrinsics/vqrdmlashq_m_n_s32.c | 24 +
.../arm/mve/intrinsics/vqrdmlashq_m_n_s8.c | 24 +
.../arm/mve/intrinsics/vqrdmlsdhq_m_s16.c | 24 +
.../arm/mve/intrinsics/vqrdmlsdhq_m_s32.c | 24 +
.../arm/mve/intrinsics/vqrdmlsdhq_m_s8.c | 24 +
.../arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c | 24 +
.../arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c | 24 +
.../arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c | 24 +
.../arm/mve/intrinsics/vqrdmulhq_m_n_s16.c | 24 +
.../arm/mve/intrinsics/vqrdmulhq_m_n_s32.c | 24 +
.../arm/mve/intrinsics/vqrdmulhq_m_n_s8.c | 24 +
.../arm/mve/intrinsics/vqrdmulhq_m_s16.c | 24 +
.../arm/mve/intrinsics/vqrdmulhq_m_s32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vqrshlq_m_s16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vqrshlq_m_s32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vqrshlq_m_s8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vqrshlq_m_u16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vqrshlq_m_u32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vqrshlq_m_u8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vqshlq_m_n_s16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vqshlq_m_n_s32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vqshlq_m_n_s8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vqshlq_m_n_u16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vqshlq_m_n_u32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vqshlq_m_n_u8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vqshlq_m_s16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vqshlq_m_s32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vqshlq_m_s8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vqshlq_m_u16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vqshlq_m_u32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vqshlq_m_u8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vrhaddq_m_s16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vrhaddq_m_s32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vrhaddq_m_s8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vrhaddq_m_u16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vrhaddq_m_u32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vrhaddq_m_u8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vrmulhq_m_s16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vrmulhq_m_s32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vrmulhq_m_s8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vrmulhq_m_u16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vrmulhq_m_u32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vrmulhq_m_u8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vrshlq_m_u16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vrshlq_m_u32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vrshlq_m_u8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vrshrq_m_n_s16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vshrq_m_n_s16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vshrq_m_n_s32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vshrq_m_n_s8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vshrq_m_n_u16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vshrq_m_n_u32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vshrq_m_n_u8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vsliq_m_n_s16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vsliq_m_n_s32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vsliq_m_n_s8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vsliq_m_n_u16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vsliq_m_n_u32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vsliq_m_n_u8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c | 24 +
305 files changed, 12527 insertions(+), 2 deletions(-)
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index eaf5ff54e45..e9e019a4a9b 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,796 @@
+2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
+ Mihail Ionescu <mihail.ionescu@arm.com>
+ Srinath Parvathaneni <srinath.parvathaneni@arm.com>
+
+ * config/arm/arm_mve.h (vabdq_m_s8): Define macro.
+ (vabdq_m_s32): Likewise.
+ (vabdq_m_s16): Likewise.
+ (vabdq_m_u8): Likewise.
+ (vabdq_m_u32): Likewise.
+ (vabdq_m_u16): Likewise.
+ (vaddq_m_n_s8): Likewise.
+ (vaddq_m_n_s32): Likewise.
+ (vaddq_m_n_s16): Likewise.
+ (vaddq_m_n_u8): Likewise.
+ (vaddq_m_n_u32): Likewise.
+ (vaddq_m_n_u16): Likewise.
+ (vaddq_m_s8): Likewise.
+ (vaddq_m_s32): Likewise.
+ (vaddq_m_s16): Likewise.
+ (vaddq_m_u8): Likewise.
+ (vaddq_m_u32): Likewise.
+ (vaddq_m_u16): Likewise.
+ (vandq_m_s8): Likewise.
+ (vandq_m_s32): Likewise.
+ (vandq_m_s16): Likewise.
+ (vandq_m_u8): Likewise.
+ (vandq_m_u32): Likewise.
+ (vandq_m_u16): Likewise.
+ (vbicq_m_s8): Likewise.
+ (vbicq_m_s32): Likewise.
+ (vbicq_m_s16): Likewise.
+ (vbicq_m_u8): Likewise.
+ (vbicq_m_u32): Likewise.
+ (vbicq_m_u16): Likewise.
+ (vbrsrq_m_n_s8): Likewise.
+ (vbrsrq_m_n_s32): Likewise.
+ (vbrsrq_m_n_s16): Likewise.
+ (vbrsrq_m_n_u8): Likewise.
+ (vbrsrq_m_n_u32): Likewise.
+ (vbrsrq_m_n_u16): Likewise.
+ (vcaddq_rot270_m_s8): Likewise.
+ (vcaddq_rot270_m_s32): Likewise.
+ (vcaddq_rot270_m_s16): Likewise.
+ (vcaddq_rot270_m_u8): Likewise.
+ (vcaddq_rot270_m_u32): Likewise.
+ (vcaddq_rot270_m_u16): Likewise.
+ (vcaddq_rot90_m_s8): Likewise.
+ (vcaddq_rot90_m_s32): Likewise.
+ (vcaddq_rot90_m_s16): Likewise.
+ (vcaddq_rot90_m_u8): Likewise.
+ (vcaddq_rot90_m_u32): Likewise.
+ (vcaddq_rot90_m_u16): Likewise.
+ (veorq_m_s8): Likewise.
+ (veorq_m_s32): Likewise.
+ (veorq_m_s16): Likewise.
+ (veorq_m_u8): Likewise.
+ (veorq_m_u32): Likewise.
+ (veorq_m_u16): Likewise.
+ (vhaddq_m_n_s8): Likewise.
+ (vhaddq_m_n_s32): Likewise.
+ (vhaddq_m_n_s16): Likewise.
+ (vhaddq_m_n_u8): Likewise.
+ (vhaddq_m_n_u32): Likewise.
+ (vhaddq_m_n_u16): Likewise.
+ (vhaddq_m_s8): Likewise.
+ (vhaddq_m_s32): Likewise.
+ (vhaddq_m_s16): Likewise.
+ (vhaddq_m_u8): Likewise.
+ (vhaddq_m_u32): Likewise.
+ (vhaddq_m_u16): Likewise.
+ (vhcaddq_rot270_m_s8): Likewise.
+ (vhcaddq_rot270_m_s32): Likewise.
+ (vhcaddq_rot270_m_s16): Likewise.
+ (vhcaddq_rot90_m_s8): Likewise.
+ (vhcaddq_rot90_m_s32): Likewise.
+ (vhcaddq_rot90_m_s16): Likewise.
+ (vhsubq_m_n_s8): Likewise.
+ (vhsubq_m_n_s32): Likewise.
+ (vhsubq_m_n_s16): Likewise.
+ (vhsubq_m_n_u8): Likewise.
+ (vhsubq_m_n_u32): Likewise.
+ (vhsubq_m_n_u16): Likewise.
+ (vhsubq_m_s8): Likewise.
+ (vhsubq_m_s32): Likewise.
+ (vhsubq_m_s16): Likewise.
+ (vhsubq_m_u8): Likewise.
+ (vhsubq_m_u32): Likewise.
+ (vhsubq_m_u16): Likewise.
+ (vmaxq_m_s8): Likewise.
+ (vmaxq_m_s32): Likewise.
+ (vmaxq_m_s16): Likewise.
+ (vmaxq_m_u8): Likewise.
+ (vmaxq_m_u32): Likewise.
+ (vmaxq_m_u16): Likewise.
+ (vminq_m_s8): Likewise.
+ (vminq_m_s32): Likewise.
+ (vminq_m_s16): Likewise.
+ (vminq_m_u8): Likewise.
+ (vminq_m_u32): Likewise.
+ (vminq_m_u16): Likewise.
+ (vmladavaq_p_s8): Likewise.
+ (vmladavaq_p_s32): Likewise.
+ (vmladavaq_p_s16): Likewise.
+ (vmladavaq_p_u8): Likewise.
+ (vmladavaq_p_u32): Likewise.
+ (vmladavaq_p_u16): Likewise.
+ (vmladavaxq_p_s8): Likewise.
+ (vmladavaxq_p_s32): Likewise.
+ (vmladavaxq_p_s16): Likewise.
+ (vmlaq_m_n_s8): Likewise.
+ (vmlaq_m_n_s32): Likewise.
+ (vmlaq_m_n_s16): Likewise.
+ (vmlaq_m_n_u8): Likewise.
+ (vmlaq_m_n_u32): Likewise.
+ (vmlaq_m_n_u16): Likewise.
+ (vmlasq_m_n_s8): Likewise.
+ (vmlasq_m_n_s32): Likewise.
+ (vmlasq_m_n_s16): Likewise.
+ (vmlasq_m_n_u8): Likewise.
+ (vmlasq_m_n_u32): Likewise.
+ (vmlasq_m_n_u16): Likewise.
+ (vmlsdavaq_p_s8): Likewise.
+ (vmlsdavaq_p_s32): Likewise.
+ (vmlsdavaq_p_s16): Likewise.
+ (vmlsdavaxq_p_s8): Likewise.
+ (vmlsdavaxq_p_s32): Likewise.
+ (vmlsdavaxq_p_s16): Likewise.
+ (vmulhq_m_s8): Likewise.
+ (vmulhq_m_s32): Likewise.
+ (vmulhq_m_s16): Likewise.
+ (vmulhq_m_u8): Likewise.
+ (vmulhq_m_u32): Likewise.
+ (vmulhq_m_u16): Likewise.
+ (vmullbq_int_m_s8): Likewise.
+ (vmullbq_int_m_s32): Likewise.
+ (vmullbq_int_m_s16): Likewise.
+ (vmullbq_int_m_u8): Likewise.
+ (vmullbq_int_m_u32): Likewise.
+ (vmullbq_int_m_u16): Likewise.
+ (vmulltq_int_m_s8): Likewise.
+ (vmulltq_int_m_s32): Likewise.
+ (vmulltq_int_m_s16): Likewise.
+ (vmulltq_int_m_u8): Likewise.
+ (vmulltq_int_m_u32): Likewise.
+ (vmulltq_int_m_u16): Likewise.
+ (vmulq_m_n_s8): Likewise.
+ (vmulq_m_n_s32): Likewise.
+ (vmulq_m_n_s16): Likewise.
+ (vmulq_m_n_u8): Likewise.
+ (vmulq_m_n_u32): Likewise.
+ (vmulq_m_n_u16): Likewise.
+ (vmulq_m_s8): Likewise.
+ (vmulq_m_s32): Likewise.
+ (vmulq_m_s16): Likewise.
+ (vmulq_m_u8): Likewise.
+ (vmulq_m_u32): Likewise.
+ (vmulq_m_u16): Likewise.
+ (vornq_m_s8): Likewise.
+ (vornq_m_s32): Likewise.
+ (vornq_m_s16): Likewise.
+ (vornq_m_u8): Likewise.
+ (vornq_m_u32): Likewise.
+ (vornq_m_u16): Likewise.
+ (vorrq_m_s8): Likewise.
+ (vorrq_m_s32): Likewise.
+ (vorrq_m_s16): Likewise.
+ (vorrq_m_u8): Likewise.
+ (vorrq_m_u32): Likewise.
+ (vorrq_m_u16): Likewise.
+ (vqaddq_m_n_s8): Likewise.
+ (vqaddq_m_n_s32): Likewise.
+ (vqaddq_m_n_s16): Likewise.
+ (vqaddq_m_n_u8): Likewise.
+ (vqaddq_m_n_u32): Likewise.
+ (vqaddq_m_n_u16): Likewise.
+ (vqaddq_m_s8): Likewise.
+ (vqaddq_m_s32): Likewise.
+ (vqaddq_m_s16): Likewise.
+ (vqaddq_m_u8): Likewise.
+ (vqaddq_m_u32): Likewise.
+ (vqaddq_m_u16): Likewise.
+ (vqdmladhq_m_s8): Likewise.
+ (vqdmladhq_m_s32): Likewise.
+ (vqdmladhq_m_s16): Likewise.
+ (vqdmladhxq_m_s8): Likewise.
+ (vqdmladhxq_m_s32): Likewise.
+ (vqdmladhxq_m_s16): Likewise.
+ (vqdmlahq_m_n_s8): Likewise.
+ (vqdmlahq_m_n_s32): Likewise.
+ (vqdmlahq_m_n_s16): Likewise.
+ (vqdmlahq_m_n_u8): Likewise.
+ (vqdmlahq_m_n_u32): Likewise.
+ (vqdmlahq_m_n_u16): Likewise.
+ (vqdmlsdhq_m_s8): Likewise.
+ (vqdmlsdhq_m_s32): Likewise.
+ (vqdmlsdhq_m_s16): Likewise.
+ (vqdmlsdhxq_m_s8): Likewise.
+ (vqdmlsdhxq_m_s32): Likewise.
+ (vqdmlsdhxq_m_s16): Likewise.
+ (vqdmulhq_m_n_s8): Likewise.
+ (vqdmulhq_m_n_s32): Likewise.
+ (vqdmulhq_m_n_s16): Likewise.
+ (vqdmulhq_m_s8): Likewise.
+ (vqdmulhq_m_s32): Likewise.
+ (vqdmulhq_m_s16): Likewise.
+ (vqrdmladhq_m_s8): Likewise.
+ (vqrdmladhq_m_s32): Likewise.
+ (vqrdmladhq_m_s16): Likewise.
+ (vqrdmladhxq_m_s8): Likewise.
+ (vqrdmladhxq_m_s32): Likewise.
+ (vqrdmladhxq_m_s16): Likewise.
+ (vqrdmlahq_m_n_s8): Likewise.
+ (vqrdmlahq_m_n_s32): Likewise.
+ (vqrdmlahq_m_n_s16): Likewise.
+ (vqrdmlahq_m_n_u8): Likewise.
+ (vqrdmlahq_m_n_u32): Likewise.
+ (vqrdmlahq_m_n_u16): Likewise.
+ (vqrdmlashq_m_n_s8): Likewise.
+ (vqrdmlashq_m_n_s32): Likewise.
+ (vqrdmlashq_m_n_s16): Likewise.
+ (vqrdmlashq_m_n_u8): Likewise.
+ (vqrdmlashq_m_n_u32): Likewise.
+ (vqrdmlashq_m_n_u16): Likewise.
+ (vqrdmlsdhq_m_s8): Likewise.
+ (vqrdmlsdhq_m_s32): Likewise.
+ (vqrdmlsdhq_m_s16): Likewise.
+ (vqrdmlsdhxq_m_s8): Likewise.
+ (vqrdmlsdhxq_m_s32): Likewise.
+ (vqrdmlsdhxq_m_s16): Likewise.
+ (vqrdmulhq_m_n_s8): Likewise.
+ (vqrdmulhq_m_n_s32): Likewise.
+ (vqrdmulhq_m_n_s16): Likewise.
+ (vqrdmulhq_m_s8): Likewise.
+ (vqrdmulhq_m_s32): Likewise.
+ (vqrdmulhq_m_s16): Likewise.
+ (vqrshlq_m_s8): Likewise.
+ (vqrshlq_m_s32): Likewise.
+ (vqrshlq_m_s16): Likewise.
+ (vqrshlq_m_u8): Likewise.
+ (vqrshlq_m_u32): Likewise.
+ (vqrshlq_m_u16): Likewise.
+ (vqshlq_m_n_s8): Likewise.
+ (vqshlq_m_n_s32): Likewise.
+ (vqshlq_m_n_s16): Likewise.
+ (vqshlq_m_n_u8): Likewise.
+ (vqshlq_m_n_u32): Likewise.
+ (vqshlq_m_n_u16): Likewise.
+ (vqshlq_m_s8): Likewise.
+ (vqshlq_m_s32): Likewise.
+ (vqshlq_m_s16): Likewise.
+ (vqshlq_m_u8): Likewise.
+ (vqshlq_m_u32): Likewise.
+ (vqshlq_m_u16): Likewise.
+ (vqsubq_m_n_s8): Likewise.
+ (vqsubq_m_n_s32): Likewise.
+ (vqsubq_m_n_s16): Likewise.
+ (vqsubq_m_n_u8): Likewise.
+ (vqsubq_m_n_u32): Likewise.
+ (vqsubq_m_n_u16): Likewise.
+ (vqsubq_m_s8): Likewise.
+ (vqsubq_m_s32): Likewise.
+ (vqsubq_m_s16): Likewise.
+ (vqsubq_m_u8): Likewise.
+ (vqsubq_m_u32): Likewise.
+ (vqsubq_m_u16): Likewise.
+ (vrhaddq_m_s8): Likewise.
+ (vrhaddq_m_s32): Likewise.
+ (vrhaddq_m_s16): Likewise.
+ (vrhaddq_m_u8): Likewise.
+ (vrhaddq_m_u32): Likewise.
+ (vrhaddq_m_u16): Likewise.
+ (vrmulhq_m_s8): Likewise.
+ (vrmulhq_m_s32): Likewise.
+ (vrmulhq_m_s16): Likewise.
+ (vrmulhq_m_u8): Likewise.
+ (vrmulhq_m_u32): Likewise.
+ (vrmulhq_m_u16): Likewise.
+ (vrshlq_m_s8): Likewise.
+ (vrshlq_m_s32): Likewise.
+ (vrshlq_m_s16): Likewise.
+ (vrshlq_m_u8): Likewise.
+ (vrshlq_m_u32): Likewise.
+ (vrshlq_m_u16): Likewise.
+ (vrshrq_m_n_s8): Likewise.
+ (vrshrq_m_n_s32): Likewise.
+ (vrshrq_m_n_s16): Likewise.
+ (vrshrq_m_n_u8): Likewise.
+ (vrshrq_m_n_u32): Likewise.
+ (vrshrq_m_n_u16): Likewise.
+ (vshlq_m_n_s8): Likewise.
+ (vshlq_m_n_s32): Likewise.
+ (vshlq_m_n_s16): Likewise.
+ (vshlq_m_n_u8): Likewise.
+ (vshlq_m_n_u32): Likewise.
+ (vshlq_m_n_u16): Likewise.
+ (vshrq_m_n_s8): Likewise.
+ (vshrq_m_n_s32): Likewise.
+ (vshrq_m_n_s16): Likewise.
+ (vshrq_m_n_u8): Likewise.
+ (vshrq_m_n_u32): Likewise.
+ (vshrq_m_n_u16): Likewise.
+ (vsliq_m_n_s8): Likewise.
+ (vsliq_m_n_s32): Likewise.
+ (vsliq_m_n_s16): Likewise.
+ (vsliq_m_n_u8): Likewise.
+ (vsliq_m_n_u32): Likewise.
+ (vsliq_m_n_u16): Likewise.
+ (vsubq_m_n_s8): Likewise.
+ (vsubq_m_n_s32): Likewise.
+ (vsubq_m_n_s16): Likewise.
+ (vsubq_m_n_u8): Likewise.
+ (vsubq_m_n_u32): Likewise.
+ (vsubq_m_n_u16): Likewise.
+ (__arm_vabdq_m_s8): Define intrinsic.
+ (__arm_vabdq_m_s32): Likewise.
+ (__arm_vabdq_m_s16): Likewise.
+ (__arm_vabdq_m_u8): Likewise.
+ (__arm_vabdq_m_u32): Likewise.
+ (__arm_vabdq_m_u16): Likewise.
+ (__arm_vaddq_m_n_s8): Likewise.
+ (__arm_vaddq_m_n_s32): Likewise.
+ (__arm_vaddq_m_n_s16): Likewise.
+ (__arm_vaddq_m_n_u8): Likewise.
+ (__arm_vaddq_m_n_u32): Likewise.
+ (__arm_vaddq_m_n_u16): Likewise.
+ (__arm_vaddq_m_s8): Likewise.
+ (__arm_vaddq_m_s32): Likewise.
+ (__arm_vaddq_m_s16): Likewise.
+ (__arm_vaddq_m_u8): Likewise.
+ (__arm_vaddq_m_u32): Likewise.
+ (__arm_vaddq_m_u16): Likewise.
+ (__arm_vandq_m_s8): Likewise.
+ (__arm_vandq_m_s32): Likewise.
+ (__arm_vandq_m_s16): Likewise.
+ (__arm_vandq_m_u8): Likewise.
+ (__arm_vandq_m_u32): Likewise.
+ (__arm_vandq_m_u16): Likewise.
+ (__arm_vbicq_m_s8): Likewise.
+ (__arm_vbicq_m_s32): Likewise.
+ (__arm_vbicq_m_s16): Likewise.
+ (__arm_vbicq_m_u8): Likewise.
+ (__arm_vbicq_m_u32): Likewise.
+ (__arm_vbicq_m_u16): Likewise.
+ (__arm_vbrsrq_m_n_s8): Likewise.
+ (__arm_vbrsrq_m_n_s32): Likewise.
+ (__arm_vbrsrq_m_n_s16): Likewise.
+ (__arm_vbrsrq_m_n_u8): Likewise.
+ (__arm_vbrsrq_m_n_u32): Likewise.
+ (__arm_vbrsrq_m_n_u16): Likewise.
+ (__arm_vcaddq_rot270_m_s8): Likewise.
+ (__arm_vcaddq_rot270_m_s32): Likewise.
+ (__arm_vcaddq_rot270_m_s16): Likewise.
+ (__arm_vcaddq_rot270_m_u8): Likewise.
+ (__arm_vcaddq_rot270_m_u32): Likewise.
+ (__arm_vcaddq_rot270_m_u16): Likewise.
+ (__arm_vcaddq_rot90_m_s8): Likewise.
+ (__arm_vcaddq_rot90_m_s32): Likewise.
+ (__arm_vcaddq_rot90_m_s16): Likewise.
+ (__arm_vcaddq_rot90_m_u8): Likewise.
+ (__arm_vcaddq_rot90_m_u32): Likewise.
+ (__arm_vcaddq_rot90_m_u16): Likewise.
+ (__arm_veorq_m_s8): Likewise.
+ (__arm_veorq_m_s32): Likewise.
+ (__arm_veorq_m_s16): Likewise.
+ (__arm_veorq_m_u8): Likewise.
+ (__arm_veorq_m_u32): Likewise.
+ (__arm_veorq_m_u16): Likewise.
+ (__arm_vhaddq_m_n_s8): Likewise.
+ (__arm_vhaddq_m_n_s32): Likewise.
+ (__arm_vhaddq_m_n_s16): Likewise.
+ (__arm_vhaddq_m_n_u8): Likewise.
+ (__arm_vhaddq_m_n_u32): Likewise.
+ (__arm_vhaddq_m_n_u16): Likewise.
+ (__arm_vhaddq_m_s8): Likewise.
+ (__arm_vhaddq_m_s32): Likewise.
+ (__arm_vhaddq_m_s16): Likewise.
+ (__arm_vhaddq_m_u8): Likewise.
+ (__arm_vhaddq_m_u32): Likewise.
+ (__arm_vhaddq_m_u16): Likewise.
+ (__arm_vhcaddq_rot270_m_s8): Likewise.
+ (__arm_vhcaddq_rot270_m_s32): Likewise.
+ (__arm_vhcaddq_rot270_m_s16): Likewise.
+ (__arm_vhcaddq_rot90_m_s8): Likewise.
+ (__arm_vhcaddq_rot90_m_s32): Likewise.
+ (__arm_vhcaddq_rot90_m_s16): Likewise.
+ (__arm_vhsubq_m_n_s8): Likewise.
+ (__arm_vhsubq_m_n_s32): Likewise.
+ (__arm_vhsubq_m_n_s16): Likewise.
+ (__arm_vhsubq_m_n_u8): Likewise.
+ (__arm_vhsubq_m_n_u32): Likewise.
+ (__arm_vhsubq_m_n_u16): Likewise.
+ (__arm_vhsubq_m_s8): Likewise.
+ (__arm_vhsubq_m_s32): Likewise.
+ (__arm_vhsubq_m_s16): Likewise.
+ (__arm_vhsubq_m_u8): Likewise.
+ (__arm_vhsubq_m_u32): Likewise.
+ (__arm_vhsubq_m_u16): Likewise.
+ (__arm_vmaxq_m_s8): Likewise.
+ (__arm_vmaxq_m_s32): Likewise.
+ (__arm_vmaxq_m_s16): Likewise.
+ (__arm_vmaxq_m_u8): Likewise.
+ (__arm_vmaxq_m_u32): Likewise.
+ (__arm_vmaxq_m_u16): Likewise.
+ (__arm_vminq_m_s8): Likewise.
+ (__arm_vminq_m_s32): Likewise.
+ (__arm_vminq_m_s16): Likewise.
+ (__arm_vminq_m_u8): Likewise.
+ (__arm_vminq_m_u32): Likewise.
+ (__arm_vminq_m_u16): Likewise.
+ (__arm_vmladavaq_p_s8): Likewise.
+ (__arm_vmladavaq_p_s32): Likewise.
+ (__arm_vmladavaq_p_s16): Likewise.
+ (__arm_vmladavaq_p_u8): Likewise.
+ (__arm_vmladavaq_p_u32): Likewise.
+ (__arm_vmladavaq_p_u16): Likewise.
+ (__arm_vmladavaxq_p_s8): Likewise.
+ (__arm_vmladavaxq_p_s32): Likewise.
+ (__arm_vmladavaxq_p_s16): Likewise.
+ (__arm_vmlaq_m_n_s8): Likewise.
+ (__arm_vmlaq_m_n_s32): Likewise.
+ (__arm_vmlaq_m_n_s16): Likewise.
+ (__arm_vmlaq_m_n_u8): Likewise.
+ (__arm_vmlaq_m_n_u32): Likewise.
+ (__arm_vmlaq_m_n_u16): Likewise.
+ (__arm_vmlasq_m_n_s8): Likewise.
+ (__arm_vmlasq_m_n_s32): Likewise.
+ (__arm_vmlasq_m_n_s16): Likewise.
+ (__arm_vmlasq_m_n_u8): Likewise.
+ (__arm_vmlasq_m_n_u32): Likewise.
+ (__arm_vmlasq_m_n_u16): Likewise.
+ (__arm_vmlsdavaq_p_s8): Likewise.
+ (__arm_vmlsdavaq_p_s32): Likewise.
+ (__arm_vmlsdavaq_p_s16): Likewise.
+ (__arm_vmlsdavaxq_p_s8): Likewise.
+ (__arm_vmlsdavaxq_p_s32): Likewise.
+ (__arm_vmlsdavaxq_p_s16): Likewise.
+ (__arm_vmulhq_m_s8): Likewise.
+ (__arm_vmulhq_m_s32): Likewise.
+ (__arm_vmulhq_m_s16): Likewise.
+ (__arm_vmulhq_m_u8): Likewise.
+ (__arm_vmulhq_m_u32): Likewise.
+ (__arm_vmulhq_m_u16): Likewise.
+ (__arm_vmullbq_int_m_s8): Likewise.
+ (__arm_vmullbq_int_m_s32): Likewise.
+ (__arm_vmullbq_int_m_s16): Likewise.
+ (__arm_vmullbq_int_m_u8): Likewise.
+ (__arm_vmullbq_int_m_u32): Likewise.
+ (__arm_vmullbq_int_m_u16): Likewise.
+ (__arm_vmulltq_int_m_s8): Likewise.
+ (__arm_vmulltq_int_m_s32): Likewise.
+ (__arm_vmulltq_int_m_s16): Likewise.
+ (__arm_vmulltq_int_m_u8): Likewise.
+ (__arm_vmulltq_int_m_u32): Likewise.
+ (__arm_vmulltq_int_m_u16): Likewise.
+ (__arm_vmulq_m_n_s8): Likewise.
+ (__arm_vmulq_m_n_s32): Likewise.
+ (__arm_vmulq_m_n_s16): Likewise.
+ (__arm_vmulq_m_n_u8): Likewise.
+ (__arm_vmulq_m_n_u32): Likewise.
+ (__arm_vmulq_m_n_u16): Likewise.
+ (__arm_vmulq_m_s8): Likewise.
+ (__arm_vmulq_m_s32): Likewise.
+ (__arm_vmulq_m_s16): Likewise.
+ (__arm_vmulq_m_u8): Likewise.
+ (__arm_vmulq_m_u32): Likewise.
+ (__arm_vmulq_m_u16): Likewise.
+ (__arm_vornq_m_s8): Likewise.
+ (__arm_vornq_m_s32): Likewise.
+ (__arm_vornq_m_s16): Likewise.
+ (__arm_vornq_m_u8): Likewise.
+ (__arm_vornq_m_u32): Likewise.
+ (__arm_vornq_m_u16): Likewise.
+ (__arm_vorrq_m_s8): Likewise.
+ (__arm_vorrq_m_s32): Likewise.
+ (__arm_vorrq_m_s16): Likewise.
+ (__arm_vorrq_m_u8): Likewise.
+ (__arm_vorrq_m_u32): Likewise.
+ (__arm_vorrq_m_u16): Likewise.
+ (__arm_vqaddq_m_n_s8): Likewise.
+ (__arm_vqaddq_m_n_s32): Likewise.
+ (__arm_vqaddq_m_n_s16): Likewise.
+ (__arm_vqaddq_m_n_u8): Likewise.
+ (__arm_vqaddq_m_n_u32): Likewise.
+ (__arm_vqaddq_m_n_u16): Likewise.
+ (__arm_vqaddq_m_s8): Likewise.
+ (__arm_vqaddq_m_s32): Likewise.
+ (__arm_vqaddq_m_s16): Likewise.
+ (__arm_vqaddq_m_u8): Likewise.
+ (__arm_vqaddq_m_u32): Likewise.
+ (__arm_vqaddq_m_u16): Likewise.
+ (__arm_vqdmladhq_m_s8): Likewise.
+ (__arm_vqdmladhq_m_s32): Likewise.
+ (__arm_vqdmladhq_m_s16): Likewise.
+ (__arm_vqdmladhxq_m_s8): Likewise.
+ (__arm_vqdmladhxq_m_s32): Likewise.
+ (__arm_vqdmladhxq_m_s16): Likewise.
+ (__arm_vqdmlahq_m_n_s8): Likewise.
+ (__arm_vqdmlahq_m_n_s32): Likewise.
+ (__arm_vqdmlahq_m_n_s16): Likewise.
+ (__arm_vqdmlahq_m_n_u8): Likewise.
+ (__arm_vqdmlahq_m_n_u32): Likewise.
+ (__arm_vqdmlahq_m_n_u16): Likewise.
+ (__arm_vqdmlsdhq_m_s8): Likewise.
+ (__arm_vqdmlsdhq_m_s32): Likewise.
+ (__arm_vqdmlsdhq_m_s16): Likewise.
+ (__arm_vqdmlsdhxq_m_s8): Likewise.
+ (__arm_vqdmlsdhxq_m_s32): Likewise.
+ (__arm_vqdmlsdhxq_m_s16): Likewise.
+ (__arm_vqdmulhq_m_n_s8): Likewise.
+ (__arm_vqdmulhq_m_n_s32): Likewise.
+ (__arm_vqdmulhq_m_n_s16): Likewise.
+ (__arm_vqdmulhq_m_s8): Likewise.
+ (__arm_vqdmulhq_m_s32): Likewise.
+ (__arm_vqdmulhq_m_s16): Likewise.
+ (__arm_vqrdmladhq_m_s8): Likewise.
+ (__arm_vqrdmladhq_m_s32): Likewise.
+ (__arm_vqrdmladhq_m_s16): Likewise.
+ (__arm_vqrdmladhxq_m_s8): Likewise.
+ (__arm_vqrdmladhxq_m_s32): Likewise.
+ (__arm_vqrdmladhxq_m_s16): Likewise.
+ (__arm_vqrdmlahq_m_n_s8): Likewise.
+ (__arm_vqrdmlahq_m_n_s32): Likewise.
+ (__arm_vqrdmlahq_m_n_s16): Likewise.
+ (__arm_vqrdmlahq_m_n_u8): Likewise.
+ (__arm_vqrdmlahq_m_n_u32): Likewise.
+ (__arm_vqrdmlahq_m_n_u16): Likewise.
+ (__arm_vqrdmlashq_m_n_s8): Likewise.
+ (__arm_vqrdmlashq_m_n_s32): Likewise.
+ (__arm_vqrdmlashq_m_n_s16): Likewise.
+ (__arm_vqrdmlashq_m_n_u8): Likewise.
+ (__arm_vqrdmlashq_m_n_u32): Likewise.
+ (__arm_vqrdmlashq_m_n_u16): Likewise.
+ (__arm_vqrdmlsdhq_m_s8): Likewise.
+ (__arm_vqrdmlsdhq_m_s32): Likewise.
+ (__arm_vqrdmlsdhq_m_s16): Likewise.
+ (__arm_vqrdmlsdhxq_m_s8): Likewise.
+ (__arm_vqrdmlsdhxq_m_s32): Likewise.
+ (__arm_vqrdmlsdhxq_m_s16): Likewise.
+ (__arm_vqrdmulhq_m_n_s8): Likewise.
+ (__arm_vqrdmulhq_m_n_s32): Likewise.
+ (__arm_vqrdmulhq_m_n_s16): Likewise.
+ (__arm_vqrdmulhq_m_s8): Likewise.
+ (__arm_vqrdmulhq_m_s32): Likewise.
+ (__arm_vqrdmulhq_m_s16): Likewise.
+ (__arm_vqrshlq_m_s8): Likewise.
+ (__arm_vqrshlq_m_s32): Likewise.
+ (__arm_vqrshlq_m_s16): Likewise.
+ (__arm_vqrshlq_m_u8): Likewise.
+ (__arm_vqrshlq_m_u32): Likewise.
+ (__arm_vqrshlq_m_u16): Likewise.
+ (__arm_vqshlq_m_n_s8): Likewise.
+ (__arm_vqshlq_m_n_s32): Likewise.
+ (__arm_vqshlq_m_n_s16): Likewise.
+ (__arm_vqshlq_m_n_u8): Likewise.
+ (__arm_vqshlq_m_n_u32): Likewise.
+ (__arm_vqshlq_m_n_u16): Likewise.
+ (__arm_vqshlq_m_s8): Likewise.
+ (__arm_vqshlq_m_s32): Likewise.
+ (__arm_vqshlq_m_s16): Likewise.
+ (__arm_vqshlq_m_u8): Likewise.
+ (__arm_vqshlq_m_u32): Likewise.
+ (__arm_vqshlq_m_u16): Likewise.
+ (__arm_vqsubq_m_n_s8): Likewise.
+ (__arm_vqsubq_m_n_s32): Likewise.
+ (__arm_vqsubq_m_n_s16): Likewise.
+ (__arm_vqsubq_m_n_u8): Likewise.
+ (__arm_vqsubq_m_n_u32): Likewise.
+ (__arm_vqsubq_m_n_u16): Likewise.
+ (__arm_vqsubq_m_s8): Likewise.
+ (__arm_vqsubq_m_s32): Likewise.
+ (__arm_vqsubq_m_s16): Likewise.
+ (__arm_vqsubq_m_u8): Likewise.
+ (__arm_vqsubq_m_u32): Likewise.
+ (__arm_vqsubq_m_u16): Likewise.
+ (__arm_vrhaddq_m_s8): Likewise.
+ (__arm_vrhaddq_m_s32): Likewise.
+ (__arm_vrhaddq_m_s16): Likewise.
+ (__arm_vrhaddq_m_u8): Likewise.
+ (__arm_vrhaddq_m_u32): Likewise.
+ (__arm_vrhaddq_m_u16): Likewise.
+ (__arm_vrmulhq_m_s8): Likewise.
+ (__arm_vrmulhq_m_s32): Likewise.
+ (__arm_vrmulhq_m_s16): Likewise.
+ (__arm_vrmulhq_m_u8): Likewise.
+ (__arm_vrmulhq_m_u32): Likewise.
+ (__arm_vrmulhq_m_u16): Likewise.
+ (__arm_vrshlq_m_s8): Likewise.
+ (__arm_vrshlq_m_s32): Likewise.
+ (__arm_vrshlq_m_s16): Likewise.
+ (__arm_vrshlq_m_u8): Likewise.
+ (__arm_vrshlq_m_u32): Likewise.
+ (__arm_vrshlq_m_u16): Likewise.
+ (__arm_vrshrq_m_n_s8): Likewise.
+ (__arm_vrshrq_m_n_s32): Likewise.
+ (__arm_vrshrq_m_n_s16): Likewise.
+ (__arm_vrshrq_m_n_u8): Likewise.
+ (__arm_vrshrq_m_n_u32): Likewise.
+ (__arm_vrshrq_m_n_u16): Likewise.
+ (__arm_vshlq_m_n_s8): Likewise.
+ (__arm_vshlq_m_n_s32): Likewise.
+ (__arm_vshlq_m_n_s16): Likewise.
+ (__arm_vshlq_m_n_u8): Likewise.
+ (__arm_vshlq_m_n_u32): Likewise.
+ (__arm_vshlq_m_n_u16): Likewise.
+ (__arm_vshrq_m_n_s8): Likewise.
+ (__arm_vshrq_m_n_s32): Likewise.
+ (__arm_vshrq_m_n_s16): Likewise.
+ (__arm_vshrq_m_n_u8): Likewise.
+ (__arm_vshrq_m_n_u32): Likewise.
+ (__arm_vshrq_m_n_u16): Likewise.
+ (__arm_vsliq_m_n_s8): Likewise.
+ (__arm_vsliq_m_n_s32): Likewise.
+ (__arm_vsliq_m_n_s16): Likewise.
+ (__arm_vsliq_m_n_u8): Likewise.
+ (__arm_vsliq_m_n_u32): Likewise.
+ (__arm_vsliq_m_n_u16): Likewise.
+ (__arm_vsubq_m_n_s8): Likewise.
+ (__arm_vsubq_m_n_s32): Likewise.
+ (__arm_vsubq_m_n_s16): Likewise.
+ (__arm_vsubq_m_n_u8): Likewise.
+ (__arm_vsubq_m_n_u32): Likewise.
+ (__arm_vsubq_m_n_u16): Likewise.
+ (vqdmladhq_m): Define polymorphic variant.
+ (vqdmladhxq_m): Likewise.
+ (vqdmlsdhq_m): Likewise.
+ (vqdmlsdhxq_m): Likewise.
+ (vabdq_m): Likewise.
+ (vandq_m): Likewise.
+ (vbicq_m): Likewise.
+ (vbrsrq_m_n): Likewise.
+ (vcaddq_rot270_m): Likewise.
+ (vcaddq_rot90_m): Likewise.
+ (veorq_m): Likewise.
+ (vmaxq_m): Likewise.
+ (vminq_m): Likewise.
+ (vmladavaq_p): Likewise.
+ (vmlaq_m_n): Likewise.
+ (vmlasq_m_n): Likewise.
+ (vmulhq_m): Likewise.
+ (vmullbq_int_m): Likewise.
+ (vmulltq_int_m): Likewise.
+ (vornq_m): Likewise.
+ (vorrq_m): Likewise.
+ (vqdmlahq_m_n): Likewise.
+ (vqrdmlahq_m_n): Likewise.
+ (vqrdmlashq_m_n): Likewise.
+ (vqrshlq_m): Likewise.
+ (vqshlq_m_n): Likewise.
+ (vqshlq_m): Likewise.
+ (vrhaddq_m): Likewise.
+ (vrmulhq_m): Likewise.
+ (vrshlq_m): Likewise.
+ (vrshrq_m_n): Likewise.
+ (vshlq_m_n): Likewise.
+ (vshrq_m_n): Likewise.
+ (vsliq_m): Likewise.
+ (vaddq_m_n): Likewise.
+ (vaddq_m): Likewise.
+ (vhaddq_m_n): Likewise.
+ (vhaddq_m): Likewise.
+ (vhcaddq_rot270_m): Likewise.
+ (vhcaddq_rot90_m): Likewise.
+ (vhsubq_m): Likewise.
+ (vhsubq_m_n): Likewise.
+ (vmulq_m_n): Likewise.
+ (vmulq_m): Likewise.
+ (vqaddq_m_n): Likewise.
+ (vqaddq_m): Likewise.
+ (vqdmulhq_m_n): Likewise.
+ (vqdmulhq_m): Likewise.
+ (vsubq_m_n): Likewise.
+ (vsliq_m_n): Likewise.
+ (vqsubq_m_n): Likewise.
+ (vqsubq_m): Likewise.
+ (vqrdmulhq_m): Likewise.
+ (vqrdmulhq_m_n): Likewise.
+ (vqrdmlsdhxq_m): Likewise.
+ (vqrdmlsdhq_m): Likewise.
+ (vqrdmladhq_m): Likewise.
+ (vqrdmladhxq_m): Likewise.
+ (vmlsdavaxq_p): Likewise.
+ (vmlsdavaq_p): Likewise.
+ (vmladavaxq_p): Likewise.
+ * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_NONE_IMM_UNONE): Use
+ builtin qualifier.
+ (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise.
+ (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE): Likewise.
+ (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE): Likewise.
+ (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE): Likewise.
+ * config/arm/mve.md (VHSUBQ_M): Define iterators.
+ (VSLIQ_M_N): Likewise.
+ (VQRDMLAHQ_M_N): Likewise.
+ (VRSHLQ_M): Likewise.
+ (VMINQ_M): Likewise.
+ (VMULLBQ_INT_M): Likewise.
+ (VMULHQ_M): Likewise.
+ (VMULQ_M): Likewise.
+ (VHSUBQ_M_N): Likewise.
+ (VHADDQ_M_N): Likewise.
+ (VORRQ_M): Likewise.
+ (VRMULHQ_M): Likewise.
+ (VQADDQ_M): Likewise.
+ (VRSHRQ_M_N): Likewise.
+ (VQSUBQ_M_N): Likewise.
+ (VADDQ_M): Likewise.
+ (VORNQ_M): Likewise.
+ (VQDMLAHQ_M_N): Likewise.
+ (VRHADDQ_M): Likewise.
+ (VQSHLQ_M): Likewise.
+ (VANDQ_M): Likewise.
+ (VBICQ_M): Likewise.
+ (VSHLQ_M_N): Likewise.
+ (VCADDQ_ROT270_M): Likewise.
+ (VQRSHLQ_M): Likewise.
+ (VQADDQ_M_N): Likewise.
+ (VADDQ_M_N): Likewise.
+ (VMAXQ_M): Likewise.
+ (VQSUBQ_M): Likewise.
+ (VMLASQ_M_N): Likewise.
+ (VMLADAVAQ_P): Likewise.
+ (VBRSRQ_M_N): Likewise.
+ (VMULQ_M_N): Likewise.
+ (VCADDQ_ROT90_M): Likewise.
+ (VMULLTQ_INT_M): Likewise.
+ (VEORQ_M): Likewise.
+ (VSHRQ_M_N): Likewise.
+ (VSUBQ_M_N): Likewise.
+ (VHADDQ_M): Likewise.
+ (VABDQ_M): Likewise.
+ (VQRDMLASHQ_M_N): Likewise.
+ (VMLAQ_M_N): Likewise.
+ (VQSHLQ_M_N): Likewise.
+ (mve_vabdq_m_<supf><mode>): Define RTL pattern.
+ (mve_vaddq_m_n_<supf><mode>): Likewise.
+ (mve_vaddq_m_<supf><mode>): Likewise.
+ (mve_vandq_m_<supf><mode>): Likewise.
+ (mve_vbicq_m_<supf><mode>): Likewise.
+ (mve_vbrsrq_m_n_<supf><mode>): Likewise.
+ (mve_vcaddq_rot270_m_<supf><mode>): Likewise.
+ (mve_vcaddq_rot90_m_<supf><mode>): Likewise.
+ (mve_veorq_m_<supf><mode>): Likewise.
+ (mve_vhaddq_m_n_<supf><mode>): Likewise.
+ (mve_vhaddq_m_<supf><mode>): Likewise.
+ (mve_vhsubq_m_n_<supf><mode>): Likewise.
+ (mve_vhsubq_m_<supf><mode>): Likewise.
+ (mve_vmaxq_m_<supf><mode>): Likewise.
+ (mve_vminq_m_<supf><mode>): Likewise.
+ (mve_vmladavaq_p_<supf><mode>): Likewise.
+ (mve_vmlaq_m_n_<supf><mode>): Likewise.
+ (mve_vmlasq_m_n_<supf><mode>): Likewise.
+ (mve_vmulhq_m_<supf><mode>): Likewise.
+ (mve_vmullbq_int_m_<supf><mode>): Likewise.
+ (mve_vmulltq_int_m_<supf><mode>): Likewise.
+ (mve_vmulq_m_n_<supf><mode>): Likewise.
+ (mve_vmulq_m_<supf><mode>): Likewise.
+ (mve_vornq_m_<supf><mode>): Likewise.
+ (mve_vorrq_m_<supf><mode>): Likewise.
+ (mve_vqaddq_m_n_<supf><mode>): Likewise.
+ (mve_vqaddq_m_<supf><mode>): Likewise.
+ (mve_vqdmlahq_m_n_<supf><mode>): Likewise.
+ (mve_vqrdmlahq_m_n_<supf><mode>): Likewise.
+ (mve_vqrdmlashq_m_n_<supf><mode>): Likewise.
+ (mve_vqrshlq_m_<supf><mode>): Likewise.
+ (mve_vqshlq_m_n_<supf><mode>): Likewise.
+ (mve_vqshlq_m_<supf><mode>): Likewise.
+ (mve_vqsubq_m_n_<supf><mode>): Likewise.
+ (mve_vqsubq_m_<supf><mode>): Likewise.
+ (mve_vrhaddq_m_<supf><mode>): Likewise.
+ (mve_vrmulhq_m_<supf><mode>): Likewise.
+ (mve_vrshlq_m_<supf><mode>): Likewise.
+ (mve_vrshrq_m_n_<supf><mode>): Likewise.
+ (mve_vshlq_m_n_<supf><mode>): Likewise.
+ (mve_vshrq_m_n_<supf><mode>): Likewise.
+ (mve_vsliq_m_n_<supf><mode>): Likewise.
+ (mve_vsubq_m_n_<supf><mode>): Likewise.
+ (mve_vhcaddq_rot270_m_s<mode>): Likewise.
+ (mve_vhcaddq_rot90_m_s<mode>): Likewise.
+ (mve_vmladavaxq_p_s<mode>): Likewise.
+ (mve_vmlsdavaq_p_s<mode>): Likewise.
+ (mve_vmlsdavaxq_p_s<mode>): Likewise.
+ (mve_vqdmladhq_m_s<mode>): Likewise.
+ (mve_vqdmladhxq_m_s<mode>): Likewise.
+ (mve_vqdmlsdhq_m_s<mode>): Likewise.
+ (mve_vqdmlsdhxq_m_s<mode>): Likewise.
+ (mve_vqdmulhq_m_n_s<mode>): Likewise.
+ (mve_vqdmulhq_m_s<mode>): Likewise.
+ (mve_vqrdmladhq_m_s<mode>): Likewise.
+ (mve_vqrdmladhxq_m_s<mode>): Likewise.
+ (mve_vqrdmlsdhq_m_s<mode>): Likewise.
+ (mve_vqrdmlsdhxq_m_s<mode>): Likewise.
+ (mve_vqrdmulhq_m_n_s<mode>): Likewise.
+ (mve_vqrdmulhq_m_s<mode>): Likewise.
+
2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
Mihail Ionescu <mihail.ionescu@arm.com>
Srinath Parvathaneni <srinath.parvathaneni@arm.com>
diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h
index e236bffa31b..53bf29e355e 100644
--- a/gcc/config/arm/arm_mve.h
+++ b/gcc/config/arm/arm_mve.h
@@ -1263,6 +1263,306 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t;
#define vsubq_m_u32(__inactive, __a, __b, __p) __arm_vsubq_m_u32(__inactive, __a, __b, __p)
#define vabavq_p_u32(__a, __b, __c, __p) __arm_vabavq_p_u32(__a, __b, __c, __p)
#define vshlq_m_s32(__inactive, __a, __b, __p) __arm_vshlq_m_s32(__inactive, __a, __b, __p)
+#define vabdq_m_s8(__inactive, __a, __b, __p) __arm_vabdq_m_s8(__inactive, __a, __b, __p)
+#define vabdq_m_s32(__inactive, __a, __b, __p) __arm_vabdq_m_s32(__inactive, __a, __b, __p)
+#define vabdq_m_s16(__inactive, __a, __b, __p) __arm_vabdq_m_s16(__inactive, __a, __b, __p)
+#define vabdq_m_u8(__inactive, __a, __b, __p) __arm_vabdq_m_u8(__inactive, __a, __b, __p)
+#define vabdq_m_u32(__inactive, __a, __b, __p) __arm_vabdq_m_u32(__inactive, __a, __b, __p)
+#define vabdq_m_u16(__inactive, __a, __b, __p) __arm_vabdq_m_u16(__inactive, __a, __b, __p)
+#define vaddq_m_n_s8(__inactive, __a, __b, __p) __arm_vaddq_m_n_s8(__inactive, __a, __b, __p)
+#define vaddq_m_n_s32(__inactive, __a, __b, __p) __arm_vaddq_m_n_s32(__inactive, __a, __b, __p)
+#define vaddq_m_n_s16(__inactive, __a, __b, __p) __arm_vaddq_m_n_s16(__inactive, __a, __b, __p)
+#define vaddq_m_n_u8(__inactive, __a, __b, __p) __arm_vaddq_m_n_u8(__inactive, __a, __b, __p)
+#define vaddq_m_n_u32(__inactive, __a, __b, __p) __arm_vaddq_m_n_u32(__inactive, __a, __b, __p)
+#define vaddq_m_n_u16(__inactive, __a, __b, __p) __arm_vaddq_m_n_u16(__inactive, __a, __b, __p)
+#define vaddq_m_s8(__inactive, __a, __b, __p) __arm_vaddq_m_s8(__inactive, __a, __b, __p)
+#define vaddq_m_s32(__inactive, __a, __b, __p) __arm_vaddq_m_s32(__inactive, __a, __b, __p)
+#define vaddq_m_s16(__inactive, __a, __b, __p) __arm_vaddq_m_s16(__inactive, __a, __b, __p)
+#define vaddq_m_u8(__inactive, __a, __b, __p) __arm_vaddq_m_u8(__inactive, __a, __b, __p)
+#define vaddq_m_u32(__inactive, __a, __b, __p) __arm_vaddq_m_u32(__inactive, __a, __b, __p)
+#define vaddq_m_u16(__inactive, __a, __b, __p) __arm_vaddq_m_u16(__inactive, __a, __b, __p)
+#define vandq_m_s8(__inactive, __a, __b, __p) __arm_vandq_m_s8(__inactive, __a, __b, __p)
+#define vandq_m_s32(__inactive, __a, __b, __p) __arm_vandq_m_s32(__inactive, __a, __b, __p)
+#define vandq_m_s16(__inactive, __a, __b, __p) __arm_vandq_m_s16(__inactive, __a, __b, __p)
+#define vandq_m_u8(__inactive, __a, __b, __p) __arm_vandq_m_u8(__inactive, __a, __b, __p)
+#define vandq_m_u32(__inactive, __a, __b, __p) __arm_vandq_m_u32(__inactive, __a, __b, __p)
+#define vandq_m_u16(__inactive, __a, __b, __p) __arm_vandq_m_u16(__inactive, __a, __b, __p)
+#define vbicq_m_s8(__inactive, __a, __b, __p) __arm_vbicq_m_s8(__inactive, __a, __b, __p)
+#define vbicq_m_s32(__inactive, __a, __b, __p) __arm_vbicq_m_s32(__inactive, __a, __b, __p)
+#define vbicq_m_s16(__inactive, __a, __b, __p) __arm_vbicq_m_s16(__inactive, __a, __b, __p)
+#define vbicq_m_u8(__inactive, __a, __b, __p) __arm_vbicq_m_u8(__inactive, __a, __b, __p)
+#define vbicq_m_u32(__inactive, __a, __b, __p) __arm_vbicq_m_u32(__inactive, __a, __b, __p)
+#define vbicq_m_u16(__inactive, __a, __b, __p) __arm_vbicq_m_u16(__inactive, __a, __b, __p)
+#define vbrsrq_m_n_s8(__inactive, __a, __b, __p) __arm_vbrsrq_m_n_s8(__inactive, __a, __b, __p)
+#define vbrsrq_m_n_s32(__inactive, __a, __b, __p) __arm_vbrsrq_m_n_s32(__inactive, __a, __b, __p)
+#define vbrsrq_m_n_s16(__inactive, __a, __b, __p) __arm_vbrsrq_m_n_s16(__inactive, __a, __b, __p)
+#define vbrsrq_m_n_u8(__inactive, __a, __b, __p) __arm_vbrsrq_m_n_u8(__inactive, __a, __b, __p)
+#define vbrsrq_m_n_u32(__inactive, __a, __b, __p) __arm_vbrsrq_m_n_u32(__inactive, __a, __b, __p)
+#define vbrsrq_m_n_u16(__inactive, __a, __b, __p) __arm_vbrsrq_m_n_u16(__inactive, __a, __b, __p)
+#define vcaddq_rot270_m_s8(__inactive, __a, __b, __p) __arm_vcaddq_rot270_m_s8(__inactive, __a, __b, __p)
+#define vcaddq_rot270_m_s32(__inactive, __a, __b, __p) __arm_vcaddq_rot270_m_s32(__inactive, __a, __b, __p)
+#define vcaddq_rot270_m_s16(__inactive, __a, __b, __p) __arm_vcaddq_rot270_m_s16(__inactive, __a, __b, __p)
+#define vcaddq_rot270_m_u8(__inactive, __a, __b, __p) __arm_vcaddq_rot270_m_u8(__inactive, __a, __b, __p)
+#define vcaddq_rot270_m_u32(__inactive, __a, __b, __p) __arm_vcaddq_rot270_m_u32(__inactive, __a, __b, __p)
+#define vcaddq_rot270_m_u16(__inactive, __a, __b, __p) __arm_vcaddq_rot270_m_u16(__inactive, __a, __b, __p)
+#define vcaddq_rot90_m_s8(__inactive, __a, __b, __p) __arm_vcaddq_rot90_m_s8(__inactive, __a, __b, __p)
+#define vcaddq_rot90_m_s32(__inactive, __a, __b, __p) __arm_vcaddq_rot90_m_s32(__inactive, __a, __b, __p)
+#define vcaddq_rot90_m_s16(__inactive, __a, __b, __p) __arm_vcaddq_rot90_m_s16(__inactive, __a, __b, __p)
+#define vcaddq_rot90_m_u8(__inactive, __a, __b, __p) __arm_vcaddq_rot90_m_u8(__inactive, __a, __b, __p)
+#define vcaddq_rot90_m_u32(__inactive, __a, __b, __p) __arm_vcaddq_rot90_m_u32(__inactive, __a, __b, __p)
+#define vcaddq_rot90_m_u16(__inactive, __a, __b, __p) __arm_vcaddq_rot90_m_u16(__inactive, __a, __b, __p)
+#define veorq_m_s8(__inactive, __a, __b, __p) __arm_veorq_m_s8(__inactive, __a, __b, __p)
+#define veorq_m_s32(__inactive, __a, __b, __p) __arm_veorq_m_s32(__inactive, __a, __b, __p)
+#define veorq_m_s16(__inactive, __a, __b, __p) __arm_veorq_m_s16(__inactive, __a, __b, __p)
+#define veorq_m_u8(__inactive, __a, __b, __p) __arm_veorq_m_u8(__inactive, __a, __b, __p)
+#define veorq_m_u32(__inactive, __a, __b, __p) __arm_veorq_m_u32(__inactive, __a, __b, __p)
+#define veorq_m_u16(__inactive, __a, __b, __p) __arm_veorq_m_u16(__inactive, __a, __b, __p)
+#define vhaddq_m_n_s8(__inactive, __a, __b, __p) __arm_vhaddq_m_n_s8(__inactive, __a, __b, __p)
+#define vhaddq_m_n_s32(__inactive, __a, __b, __p) __arm_vhaddq_m_n_s32(__inactive, __a, __b, __p)
+#define vhaddq_m_n_s16(__inactive, __a, __b, __p) __arm_vhaddq_m_n_s16(__inactive, __a, __b, __p)
+#define vhaddq_m_n_u8(__inactive, __a, __b, __p) __arm_vhaddq_m_n_u8(__inactive, __a, __b, __p)
+#define vhaddq_m_n_u32(__inactive, __a, __b, __p) __arm_vhaddq_m_n_u32(__inactive, __a, __b, __p)
+#define vhaddq_m_n_u16(__inactive, __a, __b, __p) __arm_vhaddq_m_n_u16(__inactive, __a, __b, __p)
+#define vhaddq_m_s8(__inactive, __a, __b, __p) __arm_vhaddq_m_s8(__inactive, __a, __b, __p)
+#define vhaddq_m_s32(__inactive, __a, __b, __p) __arm_vhaddq_m_s32(__inactive, __a, __b, __p)
+#define vhaddq_m_s16(__inactive, __a, __b, __p) __arm_vhaddq_m_s16(__inactive, __a, __b, __p)
+#define vhaddq_m_u8(__inactive, __a, __b, __p) __arm_vhaddq_m_u8(__inactive, __a, __b, __p)
+#define vhaddq_m_u32(__inactive, __a, __b, __p) __arm_vhaddq_m_u32(__inactive, __a, __b, __p)
+#define vhaddq_m_u16(__inactive, __a, __b, __p) __arm_vhaddq_m_u16(__inactive, __a, __b, __p)
+#define vhcaddq_rot270_m_s8(__inactive, __a, __b, __p) __arm_vhcaddq_rot270_m_s8(__inactive, __a, __b, __p)
+#define vhcaddq_rot270_m_s32(__inactive, __a, __b, __p) __arm_vhcaddq_rot270_m_s32(__inactive, __a, __b, __p)
+#define vhcaddq_rot270_m_s16(__inactive, __a, __b, __p) __arm_vhcaddq_rot270_m_s16(__inactive, __a, __b, __p)
+#define vhcaddq_rot90_m_s8(__inactive, __a, __b, __p) __arm_vhcaddq_rot90_m_s8(__inactive, __a, __b, __p)
+#define vhcaddq_rot90_m_s32(__inactive, __a, __b, __p) __arm_vhcaddq_rot90_m_s32(__inactive, __a, __b, __p)
+#define vhcaddq_rot90_m_s16(__inactive, __a, __b, __p) __arm_vhcaddq_rot90_m_s16(__inactive, __a, __b, __p)
+#define vhsubq_m_n_s8(__inactive, __a, __b, __p) __arm_vhsubq_m_n_s8(__inactive, __a, __b, __p)
+#define vhsubq_m_n_s32(__inactive, __a, __b, __p) __arm_vhsubq_m_n_s32(__inactive, __a, __b, __p)
+#define vhsubq_m_n_s16(__inactive, __a, __b, __p) __arm_vhsubq_m_n_s16(__inactive, __a, __b, __p)
+#define vhsubq_m_n_u8(__inactive, __a, __b, __p) __arm_vhsubq_m_n_u8(__inactive, __a, __b, __p)
+#define vhsubq_m_n_u32(__inactive, __a, __b, __p) __arm_vhsubq_m_n_u32(__inactive, __a, __b, __p)
+#define vhsubq_m_n_u16(__inactive, __a, __b, __p) __arm_vhsubq_m_n_u16(__inactive, __a, __b, __p)
+#define vhsubq_m_s8(__inactive, __a, __b, __p) __arm_vhsubq_m_s8(__inactive, __a, __b, __p)
+#define vhsubq_m_s32(__inactive, __a, __b, __p) __arm_vhsubq_m_s32(__inactive, __a, __b, __p)
+#define vhsubq_m_s16(__inactive, __a, __b, __p) __arm_vhsubq_m_s16(__inactive, __a, __b, __p)
+#define vhsubq_m_u8(__inactive, __a, __b, __p) __arm_vhsubq_m_u8(__inactive, __a, __b, __p)
+#define vhsubq_m_u32(__inactive, __a, __b, __p) __arm_vhsubq_m_u32(__inactive, __a, __b, __p)
+#define vhsubq_m_u16(__inactive, __a, __b, __p) __arm_vhsubq_m_u16(__inactive, __a, __b, __p)
+#define vmaxq_m_s8(__inactive, __a, __b, __p) __arm_vmaxq_m_s8(__inactive, __a, __b, __p)
+#define vmaxq_m_s32(__inactive, __a, __b, __p) __arm_vmaxq_m_s32(__inactive, __a, __b, __p)
+#define vmaxq_m_s16(__inactive, __a, __b, __p) __arm_vmaxq_m_s16(__inactive, __a, __b, __p)
+#define vmaxq_m_u8(__inactive, __a, __b, __p) __arm_vmaxq_m_u8(__inactive, __a, __b, __p)
+#define vmaxq_m_u32(__inactive, __a, __b, __p) __arm_vmaxq_m_u32(__inactive, __a, __b, __p)
+#define vmaxq_m_u16(__inactive, __a, __b, __p) __arm_vmaxq_m_u16(__inactive, __a, __b, __p)
+#define vminq_m_s8(__inactive, __a, __b, __p) __arm_vminq_m_s8(__inactive, __a, __b, __p)
+#define vminq_m_s32(__inactive, __a, __b, __p) __arm_vminq_m_s32(__inactive, __a, __b, __p)
+#define vminq_m_s16(__inactive, __a, __b, __p) __arm_vminq_m_s16(__inactive, __a, __b, __p)
+#define vminq_m_u8(__inactive, __a, __b, __p) __arm_vminq_m_u8(__inactive, __a, __b, __p)
+#define vminq_m_u32(__inactive, __a, __b, __p) __arm_vminq_m_u32(__inactive, __a, __b, __p)
+#define vminq_m_u16(__inactive, __a, __b, __p) __arm_vminq_m_u16(__inactive, __a, __b, __p)
+#define vmladavaq_p_s8(__a, __b, __c, __p) __arm_vmladavaq_p_s8(__a, __b, __c, __p)
+#define vmladavaq_p_s32(__a, __b, __c, __p) __arm_vmladavaq_p_s32(__a, __b, __c, __p)
+#define vmladavaq_p_s16(__a, __b, __c, __p) __arm_vmladavaq_p_s16(__a, __b, __c, __p)
+#define vmladavaq_p_u8(__a, __b, __c, __p) __arm_vmladavaq_p_u8(__a, __b, __c, __p)
+#define vmladavaq_p_u32(__a, __b, __c, __p) __arm_vmladavaq_p_u32(__a, __b, __c, __p)
+#define vmladavaq_p_u16(__a, __b, __c, __p) __arm_vmladavaq_p_u16(__a, __b, __c, __p)
+#define vmladavaxq_p_s8(__a, __b, __c, __p) __arm_vmladavaxq_p_s8(__a, __b, __c, __p)
+#define vmladavaxq_p_s32(__a, __b, __c, __p) __arm_vmladavaxq_p_s32(__a, __b, __c, __p)
+#define vmladavaxq_p_s16(__a, __b, __c, __p) __arm_vmladavaxq_p_s16(__a, __b, __c, __p)
+#define vmlaq_m_n_s8(__a, __b, __c, __p) __arm_vmlaq_m_n_s8(__a, __b, __c, __p)
+#define vmlaq_m_n_s32(__a, __b, __c, __p) __arm_vmlaq_m_n_s32(__a, __b, __c, __p)
+#define vmlaq_m_n_s16(__a, __b, __c, __p) __arm_vmlaq_m_n_s16(__a, __b, __c, __p)
+#define vmlaq_m_n_u8(__a, __b, __c, __p) __arm_vmlaq_m_n_u8(__a, __b, __c, __p)
+#define vmlaq_m_n_u32(__a, __b, __c, __p) __arm_vmlaq_m_n_u32(__a, __b, __c, __p)
+#define vmlaq_m_n_u16(__a, __b, __c, __p) __arm_vmlaq_m_n_u16(__a, __b, __c, __p)
+#define vmlasq_m_n_s8(__a, __b, __c, __p) __arm_vmlasq_m_n_s8(__a, __b, __c, __p)
+#define vmlasq_m_n_s32(__a, __b, __c, __p) __arm_vmlasq_m_n_s32(__a, __b, __c, __p)
+#define vmlasq_m_n_s16(__a, __b, __c, __p) __arm_vmlasq_m_n_s16(__a, __b, __c, __p)
+#define vmlasq_m_n_u8(__a, __b, __c, __p) __arm_vmlasq_m_n_u8(__a, __b, __c, __p)
+#define vmlasq_m_n_u32(__a, __b, __c, __p) __arm_vmlasq_m_n_u32(__a, __b, __c, __p)
+#define vmlasq_m_n_u16(__a, __b, __c, __p) __arm_vmlasq_m_n_u16(__a, __b, __c, __p)
+#define vmlsdavaq_p_s8(__a, __b, __c, __p) __arm_vmlsdavaq_p_s8(__a, __b, __c, __p)
+#define vmlsdavaq_p_s32(__a, __b, __c, __p) __arm_vmlsdavaq_p_s32(__a, __b, __c, __p)
+#define vmlsdavaq_p_s16(__a, __b, __c, __p) __arm_vmlsdavaq_p_s16(__a, __b, __c, __p)
+#define vmlsdavaxq_p_s8(__a, __b, __c, __p) __arm_vmlsdavaxq_p_s8(__a, __b, __c, __p)
+#define vmlsdavaxq_p_s32(__a, __b, __c, __p) __arm_vmlsdavaxq_p_s32(__a, __b, __c, __p)
+#define vmlsdavaxq_p_s16(__a, __b, __c, __p) __arm_vmlsdavaxq_p_s16(__a, __b, __c, __p)
+#define vmulhq_m_s8(__inactive, __a, __b, __p) __arm_vmulhq_m_s8(__inactive, __a, __b, __p)
+#define vmulhq_m_s32(__inactive, __a, __b, __p) __arm_vmulhq_m_s32(__inactive, __a, __b, __p)
+#define vmulhq_m_s16(__inactive, __a, __b, __p) __arm_vmulhq_m_s16(__inactive, __a, __b, __p)
+#define vmulhq_m_u8(__inactive, __a, __b, __p) __arm_vmulhq_m_u8(__inactive, __a, __b, __p)
+#define vmulhq_m_u32(__inactive, __a, __b, __p) __arm_vmulhq_m_u32(__inactive, __a, __b, __p)
+#define vmulhq_m_u16(__inactive, __a, __b, __p) __arm_vmulhq_m_u16(__inactive, __a, __b, __p)
+#define vmullbq_int_m_s8(__inactive, __a, __b, __p) __arm_vmullbq_int_m_s8(__inactive, __a, __b, __p)
+#define vmullbq_int_m_s32(__inactive, __a, __b, __p) __arm_vmullbq_int_m_s32(__inactive, __a, __b, __p)
+#define vmullbq_int_m_s16(__inactive, __a, __b, __p) __arm_vmullbq_int_m_s16(__inactive, __a, __b, __p)
+#define vmullbq_int_m_u8(__inactive, __a, __b, __p) __arm_vmullbq_int_m_u8(__inactive, __a, __b, __p)
+#define vmullbq_int_m_u32(__inactive, __a, __b, __p) __arm_vmullbq_int_m_u32(__inactive, __a, __b, __p)
+#define vmullbq_int_m_u16(__inactive, __a, __b, __p) __arm_vmullbq_int_m_u16(__inactive, __a, __b, __p)
+#define vmulltq_int_m_s8(__inactive, __a, __b, __p) __arm_vmulltq_int_m_s8(__inactive, __a, __b, __p)
+#define vmulltq_int_m_s32(__inactive, __a, __b, __p) __arm_vmulltq_int_m_s32(__inactive, __a, __b, __p)
+#define vmulltq_int_m_s16(__inactive, __a, __b, __p) __arm_vmulltq_int_m_s16(__inactive, __a, __b, __p)
+#define vmulltq_int_m_u8(__inactive, __a, __b, __p) __arm_vmulltq_int_m_u8(__inactive, __a, __b, __p)
+#define vmulltq_int_m_u32(__inactive, __a, __b, __p) __arm_vmulltq_int_m_u32(__inactive, __a, __b, __p)
+#define vmulltq_int_m_u16(__inactive, __a, __b, __p) __arm_vmulltq_int_m_u16(__inactive, __a, __b, __p)
+#define vmulq_m_n_s8(__inactive, __a, __b, __p) __arm_vmulq_m_n_s8(__inactive, __a, __b, __p)
+#define vmulq_m_n_s32(__inactive, __a, __b, __p) __arm_vmulq_m_n_s32(__inactive, __a, __b, __p)
+#define vmulq_m_n_s16(__inactive, __a, __b, __p) __arm_vmulq_m_n_s16(__inactive, __a, __b, __p)
+#define vmulq_m_n_u8(__inactive, __a, __b, __p) __arm_vmulq_m_n_u8(__inactive, __a, __b, __p)
+#define vmulq_m_n_u32(__inactive, __a, __b, __p) __arm_vmulq_m_n_u32(__inactive, __a, __b, __p)
+#define vmulq_m_n_u16(__inactive, __a, __b, __p) __arm_vmulq_m_n_u16(__inactive, __a, __b, __p)
+#define vmulq_m_s8(__inactive, __a, __b, __p) __arm_vmulq_m_s8(__inactive, __a, __b, __p)
+#define vmulq_m_s32(__inactive, __a, __b, __p) __arm_vmulq_m_s32(__inactive, __a, __b, __p)
+#define vmulq_m_s16(__inactive, __a, __b, __p) __arm_vmulq_m_s16(__inactive, __a, __b, __p)
+#define vmulq_m_u8(__inactive, __a, __b, __p) __arm_vmulq_m_u8(__inactive, __a, __b, __p)
+#define vmulq_m_u32(__inactive, __a, __b, __p) __arm_vmulq_m_u32(__inactive, __a, __b, __p)
+#define vmulq_m_u16(__inactive, __a, __b, __p) __arm_vmulq_m_u16(__inactive, __a, __b, __p)
+#define vornq_m_s8(__inactive, __a, __b, __p) __arm_vornq_m_s8(__inactive, __a, __b, __p)
+#define vornq_m_s32(__inactive, __a, __b, __p) __arm_vornq_m_s32(__inactive, __a, __b, __p)
+#define vornq_m_s16(__inactive, __a, __b, __p) __arm_vornq_m_s16(__inactive, __a, __b, __p)
+#define vornq_m_u8(__inactive, __a, __b, __p) __arm_vornq_m_u8(__inactive, __a, __b, __p)
+#define vornq_m_u32(__inactive, __a, __b, __p) __arm_vornq_m_u32(__inactive, __a, __b, __p)
+#define vornq_m_u16(__inactive, __a, __b, __p) __arm_vornq_m_u16(__inactive, __a, __b, __p)
+#define vorrq_m_s8(__inactive, __a, __b, __p) __arm_vorrq_m_s8(__inactive, __a, __b, __p)
+#define vorrq_m_s32(__inactive, __a, __b, __p) __arm_vorrq_m_s32(__inactive, __a, __b, __p)
+#define vorrq_m_s16(__inactive, __a, __b, __p) __arm_vorrq_m_s16(__inactive, __a, __b, __p)
+#define vorrq_m_u8(__inactive, __a, __b, __p) __arm_vorrq_m_u8(__inactive, __a, __b, __p)
+#define vorrq_m_u32(__inactive, __a, __b, __p) __arm_vorrq_m_u32(__inactive, __a, __b, __p)
+#define vorrq_m_u16(__inactive, __a, __b, __p) __arm_vorrq_m_u16(__inactive, __a, __b, __p)
+#define vqaddq_m_n_s8(__inactive, __a, __b, __p) __arm_vqaddq_m_n_s8(__inactive, __a, __b, __p)
+#define vqaddq_m_n_s32(__inactive, __a, __b, __p) __arm_vqaddq_m_n_s32(__inactive, __a, __b, __p)
+#define vqaddq_m_n_s16(__inactive, __a, __b, __p) __arm_vqaddq_m_n_s16(__inactive, __a, __b, __p)
+#define vqaddq_m_n_u8(__inactive, __a, __b, __p) __arm_vqaddq_m_n_u8(__inactive, __a, __b, __p)
+#define vqaddq_m_n_u32(__inactive, __a, __b, __p) __arm_vqaddq_m_n_u32(__inactive, __a, __b, __p)
+#define vqaddq_m_n_u16(__inactive, __a, __b, __p) __arm_vqaddq_m_n_u16(__inactive, __a, __b, __p)
+#define vqaddq_m_s8(__inactive, __a, __b, __p) __arm_vqaddq_m_s8(__inactive, __a, __b, __p)
+#define vqaddq_m_s32(__inactive, __a, __b, __p) __arm_vqaddq_m_s32(__inactive, __a, __b, __p)
+#define vqaddq_m_s16(__inactive, __a, __b, __p) __arm_vqaddq_m_s16(__inactive, __a, __b, __p)
+#define vqaddq_m_u8(__inactive, __a, __b, __p) __arm_vqaddq_m_u8(__inactive, __a, __b, __p)
+#define vqaddq_m_u32(__inactive, __a, __b, __p) __arm_vqaddq_m_u32(__inactive, __a, __b, __p)
+#define vqaddq_m_u16(__inactive, __a, __b, __p) __arm_vqaddq_m_u16(__inactive, __a, __b, __p)
+#define vqdmladhq_m_s8(__inactive, __a, __b, __p) __arm_vqdmladhq_m_s8(__inactive, __a, __b, __p)
+#define vqdmladhq_m_s32(__inactive, __a, __b, __p) __arm_vqdmladhq_m_s32(__inactive, __a, __b, __p)
+#define vqdmladhq_m_s16(__inactive, __a, __b, __p) __arm_vqdmladhq_m_s16(__inactive, __a, __b, __p)
+#define vqdmladhxq_m_s8(__inactive, __a, __b, __p) __arm_vqdmladhxq_m_s8(__inactive, __a, __b, __p)
+#define vqdmladhxq_m_s32(__inactive, __a, __b, __p) __arm_vqdmladhxq_m_s32(__inactive, __a, __b, __p)
+#define vqdmladhxq_m_s16(__inactive, __a, __b, __p) __arm_vqdmladhxq_m_s16(__inactive, __a, __b, __p)
+#define vqdmlahq_m_n_s8(__a, __b, __c, __p) __arm_vqdmlahq_m_n_s8(__a, __b, __c, __p)
+#define vqdmlahq_m_n_s32(__a, __b, __c, __p) __arm_vqdmlahq_m_n_s32(__a, __b, __c, __p)
+#define vqdmlahq_m_n_s16(__a, __b, __c, __p) __arm_vqdmlahq_m_n_s16(__a, __b, __c, __p)
+#define vqdmlsdhq_m_s8(__inactive, __a, __b, __p) __arm_vqdmlsdhq_m_s8(__inactive, __a, __b, __p)
+#define vqdmlsdhq_m_s32(__inactive, __a, __b, __p) __arm_vqdmlsdhq_m_s32(__inactive, __a, __b, __p)
+#define vqdmlsdhq_m_s16(__inactive, __a, __b, __p) __arm_vqdmlsdhq_m_s16(__inactive, __a, __b, __p)
+#define vqdmlsdhxq_m_s8(__inactive, __a, __b, __p) __arm_vqdmlsdhxq_m_s8(__inactive, __a, __b, __p)
+#define vqdmlsdhxq_m_s32(__inactive, __a, __b, __p) __arm_vqdmlsdhxq_m_s32(__inactive, __a, __b, __p)
+#define vqdmlsdhxq_m_s16(__inactive, __a, __b, __p) __arm_vqdmlsdhxq_m_s16(__inactive, __a, __b, __p)
+#define vqdmulhq_m_n_s8(__inactive, __a, __b, __p) __arm_vqdmulhq_m_n_s8(__inactive, __a, __b, __p)
+#define vqdmulhq_m_n_s32(__inactive, __a, __b, __p) __arm_vqdmulhq_m_n_s32(__inactive, __a, __b, __p)
+#define vqdmulhq_m_n_s16(__inactive, __a, __b, __p) __arm_vqdmulhq_m_n_s16(__inactive, __a, __b, __p)
+#define vqdmulhq_m_s8(__inactive, __a, __b, __p) __arm_vqdmulhq_m_s8(__inactive, __a, __b, __p)
+#define vqdmulhq_m_s32(__inactive, __a, __b, __p) __arm_vqdmulhq_m_s32(__inactive, __a, __b, __p)
+#define vqdmulhq_m_s16(__inactive, __a, __b, __p) __arm_vqdmulhq_m_s16(__inactive, __a, __b, __p)
+#define vqrdmladhq_m_s8(__inactive, __a, __b, __p) __arm_vqrdmladhq_m_s8(__inactive, __a, __b, __p)
+#define vqrdmladhq_m_s32(__inactive, __a, __b, __p) __arm_vqrdmladhq_m_s32(__inactive, __a, __b, __p)
+#define vqrdmladhq_m_s16(__inactive, __a, __b, __p) __arm_vqrdmladhq_m_s16(__inactive, __a, __b, __p)
+#define vqrdmladhxq_m_s8(__inactive, __a, __b, __p) __arm_vqrdmladhxq_m_s8(__inactive, __a, __b, __p)
+#define vqrdmladhxq_m_s32(__inactive, __a, __b, __p) __arm_vqrdmladhxq_m_s32(__inactive, __a, __b, __p)
+#define vqrdmladhxq_m_s16(__inactive, __a, __b, __p) __arm_vqrdmladhxq_m_s16(__inactive, __a, __b, __p)
+#define vqrdmlahq_m_n_s8(__a, __b, __c, __p) __arm_vqrdmlahq_m_n_s8(__a, __b, __c, __p)
+#define vqrdmlahq_m_n_s32(__a, __b, __c, __p) __arm_vqrdmlahq_m_n_s32(__a, __b, __c, __p)
+#define vqrdmlahq_m_n_s16(__a, __b, __c, __p) __arm_vqrdmlahq_m_n_s16(__a, __b, __c, __p)
+#define vqrdmlashq_m_n_s8(__a, __b, __c, __p) __arm_vqrdmlashq_m_n_s8(__a, __b, __c, __p)
+#define vqrdmlashq_m_n_s32(__a, __b, __c, __p) __arm_vqrdmlashq_m_n_s32(__a, __b, __c, __p)
+#define vqrdmlashq_m_n_s16(__a, __b, __c, __p) __arm_vqrdmlashq_m_n_s16(__a, __b, __c, __p)
+#define vqrdmlsdhq_m_s8(__inactive, __a, __b, __p) __arm_vqrdmlsdhq_m_s8(__inactive, __a, __b, __p)
+#define vqrdmlsdhq_m_s32(__inactive, __a, __b, __p) __arm_vqrdmlsdhq_m_s32(__inactive, __a, __b, __p)
+#define vqrdmlsdhq_m_s16(__inactive, __a, __b, __p) __arm_vqrdmlsdhq_m_s16(__inactive, __a, __b, __p)
+#define vqrdmlsdhxq_m_s8(__inactive, __a, __b, __p) __arm_vqrdmlsdhxq_m_s8(__inactive, __a, __b, __p)
+#define vqrdmlsdhxq_m_s32(__inactive, __a, __b, __p) __arm_vqrdmlsdhxq_m_s32(__inactive, __a, __b, __p)
+#define vqrdmlsdhxq_m_s16(__inactive, __a, __b, __p) __arm_vqrdmlsdhxq_m_s16(__inactive, __a, __b, __p)
+#define vqrdmulhq_m_n_s8(__inactive, __a, __b, __p) __arm_vqrdmulhq_m_n_s8(__inactive, __a, __b, __p)
+#define vqrdmulhq_m_n_s32(__inactive, __a, __b, __p) __arm_vqrdmulhq_m_n_s32(__inactive, __a, __b, __p)
+#define vqrdmulhq_m_n_s16(__inactive, __a, __b, __p) __arm_vqrdmulhq_m_n_s16(__inactive, __a, __b, __p)
+#define vqrdmulhq_m_s8(__inactive, __a, __b, __p) __arm_vqrdmulhq_m_s8(__inactive, __a, __b, __p)
+#define vqrdmulhq_m_s32(__inactive, __a, __b, __p) __arm_vqrdmulhq_m_s32(__inactive, __a, __b, __p)
+#define vqrdmulhq_m_s16(__inactive, __a, __b, __p) __arm_vqrdmulhq_m_s16(__inactive, __a, __b, __p)
+#define vqrshlq_m_s8(__inactive, __a, __b, __p) __arm_vqrshlq_m_s8(__inactive, __a, __b, __p)
+#define vqrshlq_m_s32(__inactive, __a, __b, __p) __arm_vqrshlq_m_s32(__inactive, __a, __b, __p)
+#define vqrshlq_m_s16(__inactive, __a, __b, __p) __arm_vqrshlq_m_s16(__inactive, __a, __b, __p)
+#define vqrshlq_m_u8(__inactive, __a, __b, __p) __arm_vqrshlq_m_u8(__inactive, __a, __b, __p)
+#define vqrshlq_m_u32(__inactive, __a, __b, __p) __arm_vqrshlq_m_u32(__inactive, __a, __b, __p)
+#define vqrshlq_m_u16(__inactive, __a, __b, __p) __arm_vqrshlq_m_u16(__inactive, __a, __b, __p)
+#define vqshlq_m_n_s8(__inactive, __a, __imm, __p) __arm_vqshlq_m_n_s8(__inactive, __a, __imm, __p)
+#define vqshlq_m_n_s32(__inactive, __a, __imm, __p) __arm_vqshlq_m_n_s32(__inactive, __a, __imm, __p)
+#define vqshlq_m_n_s16(__inactive, __a, __imm, __p) __arm_vqshlq_m_n_s16(__inactive, __a, __imm, __p)
+#define vqshlq_m_n_u8(__inactive, __a, __imm, __p) __arm_vqshlq_m_n_u8(__inactive, __a, __imm, __p)
+#define vqshlq_m_n_u32(__inactive, __a, __imm, __p) __arm_vqshlq_m_n_u32(__inactive, __a, __imm, __p)
+#define vqshlq_m_n_u16(__inactive, __a, __imm, __p) __arm_vqshlq_m_n_u16(__inactive, __a, __imm, __p)
+#define vqshlq_m_s8(__inactive, __a, __b, __p) __arm_vqshlq_m_s8(__inactive, __a, __b, __p)
+#define vqshlq_m_s32(__inactive, __a, __b, __p) __arm_vqshlq_m_s32(__inactive, __a, __b, __p)
+#define vqshlq_m_s16(__inactive, __a, __b, __p) __arm_vqshlq_m_s16(__inactive, __a, __b, __p)
+#define vqshlq_m_u8(__inactive, __a, __b, __p) __arm_vqshlq_m_u8(__inactive, __a, __b, __p)
+#define vqshlq_m_u32(__inactive, __a, __b, __p) __arm_vqshlq_m_u32(__inactive, __a, __b, __p)
+#define vqshlq_m_u16(__inactive, __a, __b, __p) __arm_vqshlq_m_u16(__inactive, __a, __b, __p)
+#define vqsubq_m_n_s8(__inactive, __a, __b, __p) __arm_vqsubq_m_n_s8(__inactive, __a, __b, __p)
+#define vqsubq_m_n_s32(__inactive, __a, __b, __p) __arm_vqsubq_m_n_s32(__inactive, __a, __b, __p)
+#define vqsubq_m_n_s16(__inactive, __a, __b, __p) __arm_vqsubq_m_n_s16(__inactive, __a, __b, __p)
+#define vqsubq_m_n_u8(__inactive, __a, __b, __p) __arm_vqsubq_m_n_u8(__inactive, __a, __b, __p)
+#define vqsubq_m_n_u32(__inactive, __a, __b, __p) __arm_vqsubq_m_n_u32(__inactive, __a, __b, __p)
+#define vqsubq_m_n_u16(__inactive, __a, __b, __p) __arm_vqsubq_m_n_u16(__inactive, __a, __b, __p)
+#define vqsubq_m_s8(__inactive, __a, __b, __p) __arm_vqsubq_m_s8(__inactive, __a, __b, __p)
+#define vqsubq_m_s32(__inactive, __a, __b, __p) __arm_vqsubq_m_s32(__inactive, __a, __b, __p)
+#define vqsubq_m_s16(__inactive, __a, __b, __p) __arm_vqsubq_m_s16(__inactive, __a, __b, __p)
+#define vqsubq_m_u8(__inactive, __a, __b, __p) __arm_vqsubq_m_u8(__inactive, __a, __b, __p)
+#define vqsubq_m_u32(__inactive, __a, __b, __p) __arm_vqsubq_m_u32(__inactive, __a, __b, __p)
+#define vqsubq_m_u16(__inactive, __a, __b, __p) __arm_vqsubq_m_u16(__inactive, __a, __b, __p)
+#define vrhaddq_m_s8(__inactive, __a, __b, __p) __arm_vrhaddq_m_s8(__inactive, __a, __b, __p)
+#define vrhaddq_m_s32(__inactive, __a, __b, __p) __arm_vrhaddq_m_s32(__inactive, __a, __b, __p)
+#define vrhaddq_m_s16(__inactive, __a, __b, __p) __arm_vrhaddq_m_s16(__inactive, __a, __b, __p)
+#define vrhaddq_m_u8(__inactive, __a, __b, __p) __arm_vrhaddq_m_u8(__inactive, __a, __b, __p)
+#define vrhaddq_m_u32(__inactive, __a, __b, __p) __arm_vrhaddq_m_u32(__inactive, __a, __b, __p)
+#define vrhaddq_m_u16(__inactive, __a, __b, __p) __arm_vrhaddq_m_u16(__inactive, __a, __b, __p)
+#define vrmulhq_m_s8(__inactive, __a, __b, __p) __arm_vrmulhq_m_s8(__inactive, __a, __b, __p)
+#define vrmulhq_m_s32(__inactive, __a, __b, __p) __arm_vrmulhq_m_s32(__inactive, __a, __b, __p)
+#define vrmulhq_m_s16(__inactive, __a, __b, __p) __arm_vrmulhq_m_s16(__inactive, __a, __b, __p)
+#define vrmulhq_m_u8(__inactive, __a, __b, __p) __arm_vrmulhq_m_u8(__inactive, __a, __b, __p)
+#define vrmulhq_m_u32(__inactive, __a, __b, __p) __arm_vrmulhq_m_u32(__inactive, __a, __b, __p)
+#define vrmulhq_m_u16(__inactive, __a, __b, __p) __arm_vrmulhq_m_u16(__inactive, __a, __b, __p)
+#define vrshlq_m_s8(__inactive, __a, __b, __p) __arm_vrshlq_m_s8(__inactive, __a, __b, __p)
+#define vrshlq_m_s32(__inactive, __a, __b, __p) __arm_vrshlq_m_s32(__inactive, __a, __b, __p)
+#define vrshlq_m_s16(__inactive, __a, __b, __p) __arm_vrshlq_m_s16(__inactive, __a, __b, __p)
+#define vrshlq_m_u8(__inactive, __a, __b, __p) __arm_vrshlq_m_u8(__inactive, __a, __b, __p)
+#define vrshlq_m_u32(__inactive, __a, __b, __p) __arm_vrshlq_m_u32(__inactive, __a, __b, __p)
+#define vrshlq_m_u16(__inactive, __a, __b, __p) __arm_vrshlq_m_u16(__inactive, __a, __b, __p)
+#define vrshrq_m_n_s8(__inactive, __a, __imm, __p) __arm_vrshrq_m_n_s8(__inactive, __a, __imm, __p)
+#define vrshrq_m_n_s32(__inactive, __a, __imm, __p) __arm_vrshrq_m_n_s32(__inactive, __a, __imm, __p)
+#define vrshrq_m_n_s16(__inactive, __a, __imm, __p) __arm_vrshrq_m_n_s16(__inactive, __a, __imm, __p)
+#define vrshrq_m_n_u8(__inactive, __a, __imm, __p) __arm_vrshrq_m_n_u8(__inactive, __a, __imm, __p)
+#define vrshrq_m_n_u32(__inactive, __a, __imm, __p) __arm_vrshrq_m_n_u32(__inactive, __a, __imm, __p)
+#define vrshrq_m_n_u16(__inactive, __a, __imm, __p) __arm_vrshrq_m_n_u16(__inactive, __a, __imm, __p)
+#define vshlq_m_n_s8(__inactive, __a, __imm, __p) __arm_vshlq_m_n_s8(__inactive, __a, __imm, __p)
+#define vshlq_m_n_s32(__inactive, __a, __imm, __p) __arm_vshlq_m_n_s32(__inactive, __a, __imm, __p)
+#define vshlq_m_n_s16(__inactive, __a, __imm, __p) __arm_vshlq_m_n_s16(__inactive, __a, __imm, __p)
+#define vshlq_m_n_u8(__inactive, __a, __imm, __p) __arm_vshlq_m_n_u8(__inactive, __a, __imm, __p)
+#define vshlq_m_n_u32(__inactive, __a, __imm, __p) __arm_vshlq_m_n_u32(__inactive, __a, __imm, __p)
+#define vshlq_m_n_u16(__inactive, __a, __imm, __p) __arm_vshlq_m_n_u16(__inactive, __a, __imm, __p)
+#define vshrq_m_n_s8(__inactive, __a, __imm, __p) __arm_vshrq_m_n_s8(__inactive, __a, __imm, __p)
+#define vshrq_m_n_s32(__inactive, __a, __imm, __p) __arm_vshrq_m_n_s32(__inactive, __a, __imm, __p)
+#define vshrq_m_n_s16(__inactive, __a, __imm, __p) __arm_vshrq_m_n_s16(__inactive, __a, __imm, __p)
+#define vshrq_m_n_u8(__inactive, __a, __imm, __p) __arm_vshrq_m_n_u8(__inactive, __a, __imm, __p)
+#define vshrq_m_n_u32(__inactive, __a, __imm, __p) __arm_vshrq_m_n_u32(__inactive, __a, __imm, __p)
+#define vshrq_m_n_u16(__inactive, __a, __imm, __p) __arm_vshrq_m_n_u16(__inactive, __a, __imm, __p)
+#define vsliq_m_n_s8(__a, __b, __imm, __p) __arm_vsliq_m_n_s8(__a, __b, __imm, __p)
+#define vsliq_m_n_s32(__a, __b, __imm, __p) __arm_vsliq_m_n_s32(__a, __b, __imm, __p)
+#define vsliq_m_n_s16(__a, __b, __imm, __p) __arm_vsliq_m_n_s16(__a, __b, __imm, __p)
+#define vsliq_m_n_u8(__a, __b, __imm, __p) __arm_vsliq_m_n_u8(__a, __b, __imm, __p)
+#define vsliq_m_n_u32(__a, __b, __imm, __p) __arm_vsliq_m_n_u32(__a, __b, __imm, __p)
+#define vsliq_m_n_u16(__a, __b, __imm, __p) __arm_vsliq_m_n_u16(__a, __b, __imm, __p)
+#define vsubq_m_n_s8(__inactive, __a, __b, __p) __arm_vsubq_m_n_s8(__inactive, __a, __b, __p)
+#define vsubq_m_n_s32(__inactive, __a, __b, __p) __arm_vsubq_m_n_s32(__inactive, __a, __b, __p)
+#define vsubq_m_n_s16(__inactive, __a, __b, __p) __arm_vsubq_m_n_s16(__inactive, __a, __b, __p)
+#define vsubq_m_n_u8(__inactive, __a, __b, __p) __arm_vsubq_m_n_u8(__inactive, __a, __b, __p)
+#define vsubq_m_n_u32(__inactive, __a, __b, __p) __arm_vsubq_m_n_u32(__inactive, __a, __b, __p)
+#define vsubq_m_n_u16(__inactive, __a, __b, __p) __arm_vsubq_m_n_u16(__inactive, __a, __b, __p)
#endif
__extension__ extern __inline void
@@ -7917,6 +8217,2106 @@ __arm_vshlq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred1
return __builtin_mve_vshlq_m_sv4si (__inactive, __a, __b, __p);
}
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vabdq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vabdq_m_sv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vabdq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vabdq_m_sv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vabdq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vabdq_m_sv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vabdq_m_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vabdq_m_uv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vabdq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vabdq_m_uv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vabdq_m_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vabdq_m_uv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vaddq_m_n_s8 (int8x16_t __inactive, int8x16_t __a, int8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vaddq_m_n_sv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vaddq_m_n_s32 (int32x4_t __inactive, int32x4_t __a, int32_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vaddq_m_n_sv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vaddq_m_n_s16 (int16x8_t __inactive, int16x8_t __a, int16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vaddq_m_n_sv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vaddq_m_n_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vaddq_m_n_uv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vaddq_m_n_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vaddq_m_n_uv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vaddq_m_n_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vaddq_m_n_uv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vaddq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vaddq_m_sv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vaddq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vaddq_m_sv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vaddq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vaddq_m_sv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vaddq_m_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vaddq_m_uv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vaddq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vaddq_m_uv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vaddq_m_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vaddq_m_uv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vandq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vandq_m_sv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vandq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vandq_m_sv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vandq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vandq_m_sv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vandq_m_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vandq_m_uv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vandq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vandq_m_uv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vandq_m_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vandq_m_uv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vbicq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vbicq_m_sv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vbicq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vbicq_m_sv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vbicq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vbicq_m_sv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vbicq_m_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vbicq_m_uv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vbicq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vbicq_m_uv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vbicq_m_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vbicq_m_uv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vbrsrq_m_n_s8 (int8x16_t __inactive, int8x16_t __a, int32_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vbrsrq_m_n_sv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vbrsrq_m_n_s32 (int32x4_t __inactive, int32x4_t __a, int32_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vbrsrq_m_n_sv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vbrsrq_m_n_s16 (int16x8_t __inactive, int16x8_t __a, int32_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vbrsrq_m_n_sv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vbrsrq_m_n_u8 (uint8x16_t __inactive, uint8x16_t __a, int32_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vbrsrq_m_n_uv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vbrsrq_m_n_u32 (uint32x4_t __inactive, uint32x4_t __a, int32_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vbrsrq_m_n_uv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vbrsrq_m_n_u16 (uint16x8_t __inactive, uint16x8_t __a, int32_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vbrsrq_m_n_uv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcaddq_rot270_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vcaddq_rot270_m_sv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcaddq_rot270_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vcaddq_rot270_m_sv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcaddq_rot270_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vcaddq_rot270_m_sv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcaddq_rot270_m_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vcaddq_rot270_m_uv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcaddq_rot270_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vcaddq_rot270_m_uv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcaddq_rot270_m_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vcaddq_rot270_m_uv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcaddq_rot90_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vcaddq_rot90_m_sv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcaddq_rot90_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vcaddq_rot90_m_sv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcaddq_rot90_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vcaddq_rot90_m_sv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcaddq_rot90_m_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vcaddq_rot90_m_uv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcaddq_rot90_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vcaddq_rot90_m_uv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcaddq_rot90_m_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vcaddq_rot90_m_uv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_veorq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_veorq_m_sv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_veorq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_veorq_m_sv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_veorq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_veorq_m_sv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_veorq_m_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_veorq_m_uv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_veorq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_veorq_m_uv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_veorq_m_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_veorq_m_uv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vhaddq_m_n_s8 (int8x16_t __inactive, int8x16_t __a, int8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vhaddq_m_n_sv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vhaddq_m_n_s32 (int32x4_t __inactive, int32x4_t __a, int32_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vhaddq_m_n_sv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vhaddq_m_n_s16 (int16x8_t __inactive, int16x8_t __a, int16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vhaddq_m_n_sv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vhaddq_m_n_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vhaddq_m_n_uv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vhaddq_m_n_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vhaddq_m_n_uv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vhaddq_m_n_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vhaddq_m_n_uv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vhaddq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vhaddq_m_sv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vhaddq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vhaddq_m_sv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vhaddq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vhaddq_m_sv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vhaddq_m_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vhaddq_m_uv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vhaddq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vhaddq_m_uv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vhaddq_m_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vhaddq_m_uv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vhcaddq_rot270_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vhcaddq_rot270_m_sv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vhcaddq_rot270_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vhcaddq_rot270_m_sv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vhcaddq_rot270_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vhcaddq_rot270_m_sv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vhcaddq_rot90_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vhcaddq_rot90_m_sv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vhcaddq_rot90_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vhcaddq_rot90_m_sv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vhcaddq_rot90_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vhcaddq_rot90_m_sv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vhsubq_m_n_s8 (int8x16_t __inactive, int8x16_t __a, int8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vhsubq_m_n_sv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vhsubq_m_n_s32 (int32x4_t __inactive, int32x4_t __a, int32_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vhsubq_m_n_sv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vhsubq_m_n_s16 (int16x8_t __inactive, int16x8_t __a, int16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vhsubq_m_n_sv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vhsubq_m_n_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vhsubq_m_n_uv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vhsubq_m_n_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vhsubq_m_n_uv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vhsubq_m_n_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vhsubq_m_n_uv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vhsubq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vhsubq_m_sv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vhsubq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vhsubq_m_sv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vhsubq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vhsubq_m_sv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vhsubq_m_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vhsubq_m_uv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vhsubq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vhsubq_m_uv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vhsubq_m_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vhsubq_m_uv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmaxq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vmaxq_m_sv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmaxq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vmaxq_m_sv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmaxq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vmaxq_m_sv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmaxq_m_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vmaxq_m_uv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmaxq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vmaxq_m_uv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmaxq_m_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vmaxq_m_uv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vminq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vminq_m_sv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vminq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vminq_m_sv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vminq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vminq_m_sv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vminq_m_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vminq_m_uv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vminq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vminq_m_uv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vminq_m_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vminq_m_uv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int32_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmladavaq_p_s8 (int32_t __a, int8x16_t __b, int8x16_t __c, mve_pred16_t __p)
+{
+ return __builtin_mve_vmladavaq_p_sv16qi (__a, __b, __c, __p);
+}
+
+__extension__ extern __inline int32_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmladavaq_p_s32 (int32_t __a, int32x4_t __b, int32x4_t __c, mve_pred16_t __p)
+{
+ return __builtin_mve_vmladavaq_p_sv4si (__a, __b, __c, __p);
+}
+
+__extension__ extern __inline int32_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmladavaq_p_s16 (int32_t __a, int16x8_t __b, int16x8_t __c, mve_pred16_t __p)
+{
+ return __builtin_mve_vmladavaq_p_sv8hi (__a, __b, __c, __p);
+}
+
+__extension__ extern __inline uint32_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmladavaq_p_u8 (uint32_t __a, uint8x16_t __b, uint8x16_t __c, mve_pred16_t __p)
+{
+ return __builtin_mve_vmladavaq_p_uv16qi (__a, __b, __c, __p);
+}
+
+__extension__ extern __inline uint32_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmladavaq_p_u32 (uint32_t __a, uint32x4_t __b, uint32x4_t __c, mve_pred16_t __p)
+{
+ return __builtin_mve_vmladavaq_p_uv4si (__a, __b, __c, __p);
+}
+
+__extension__ extern __inline uint32_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmladavaq_p_u16 (uint32_t __a, uint16x8_t __b, uint16x8_t __c, mve_pred16_t __p)
+{
+ return __builtin_mve_vmladavaq_p_uv8hi (__a, __b, __c, __p);
+}
+
+__extension__ extern __inline int32_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmladavaxq_p_s8 (int32_t __a, int8x16_t __b, int8x16_t __c, mve_pred16_t __p)
+{
+ return __builtin_mve_vmladavaxq_p_sv16qi (__a, __b, __c, __p);
+}
+
+__extension__ extern __inline int32_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmladavaxq_p_s32 (int32_t __a, int32x4_t __b, int32x4_t __c, mve_pred16_t __p)
+{
+ return __builtin_mve_vmladavaxq_p_sv4si (__a, __b, __c, __p);
+}
+
+__extension__ extern __inline int32_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmladavaxq_p_s16 (int32_t __a, int16x8_t __b, int16x8_t __c, mve_pred16_t __p)
+{
+ return __builtin_mve_vmladavaxq_p_sv8hi (__a, __b, __c, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmlaq_m_n_s8 (int8x16_t __a, int8x16_t __b, int8_t __c, mve_pred16_t __p)
+{
+ return __builtin_mve_vmlaq_m_n_sv16qi (__a, __b, __c, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmlaq_m_n_s32 (int32x4_t __a, int32x4_t __b, int32_t __c, mve_pred16_t __p)
+{
+ return __builtin_mve_vmlaq_m_n_sv4si (__a, __b, __c, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmlaq_m_n_s16 (int16x8_t __a, int16x8_t __b, int16_t __c, mve_pred16_t __p)
+{
+ return __builtin_mve_vmlaq_m_n_sv8hi (__a, __b, __c, __p);
+}
+
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmlaq_m_n_u8 (uint8x16_t __a, uint8x16_t __b, uint8_t __c, mve_pred16_t __p)
+{
+ return __builtin_mve_vmlaq_m_n_uv16qi (__a, __b, __c, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmlaq_m_n_u32 (uint32x4_t __a, uint32x4_t __b, uint32_t __c, mve_pred16_t __p)
+{
+ return __builtin_mve_vmlaq_m_n_uv4si (__a, __b, __c, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmlaq_m_n_u16 (uint16x8_t __a, uint16x8_t __b, uint16_t __c, mve_pred16_t __p)
+{
+ return __builtin_mve_vmlaq_m_n_uv8hi (__a, __b, __c, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmlasq_m_n_s8 (int8x16_t __a, int8x16_t __b, int8_t __c, mve_pred16_t __p)
+{
+ return __builtin_mve_vmlasq_m_n_sv16qi (__a, __b, __c, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmlasq_m_n_s32 (int32x4_t __a, int32x4_t __b, int32_t __c, mve_pred16_t __p)
+{
+ return __builtin_mve_vmlasq_m_n_sv4si (__a, __b, __c, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmlasq_m_n_s16 (int16x8_t __a, int16x8_t __b, int16_t __c, mve_pred16_t __p)
+{
+ return __builtin_mve_vmlasq_m_n_sv8hi (__a, __b, __c, __p);
+}
+
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmlasq_m_n_u8 (uint8x16_t __a, uint8x16_t __b, uint8_t __c, mve_pred16_t __p)
+{
+ return __builtin_mve_vmlasq_m_n_uv16qi (__a, __b, __c, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmlasq_m_n_u32 (uint32x4_t __a, uint32x4_t __b, uint32_t __c, mve_pred16_t __p)
+{
+ return __builtin_mve_vmlasq_m_n_uv4si (__a, __b, __c, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmlasq_m_n_u16 (uint16x8_t __a, uint16x8_t __b, uint16_t __c, mve_pred16_t __p)
+{
+ return __builtin_mve_vmlasq_m_n_uv8hi (__a, __b, __c, __p);
+}
+
+__extension__ extern __inline int32_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmlsdavaq_p_s8 (int32_t __a, int8x16_t __b, int8x16_t __c, mve_pred16_t __p)
+{
+ return __builtin_mve_vmlsdavaq_p_sv16qi (__a, __b, __c, __p);
+}
+
+__extension__ extern __inline int32_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmlsdavaq_p_s32 (int32_t __a, int32x4_t __b, int32x4_t __c, mve_pred16_t __p)
+{
+ return __builtin_mve_vmlsdavaq_p_sv4si (__a, __b, __c, __p);
+}
+
+__extension__ extern __inline int32_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmlsdavaq_p_s16 (int32_t __a, int16x8_t __b, int16x8_t __c, mve_pred16_t __p)
+{
+ return __builtin_mve_vmlsdavaq_p_sv8hi (__a, __b, __c, __p);
+}
+
+__extension__ extern __inline int32_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmlsdavaxq_p_s8 (int32_t __a, int8x16_t __b, int8x16_t __c, mve_pred16_t __p)
+{
+ return __builtin_mve_vmlsdavaxq_p_sv16qi (__a, __b, __c, __p);
+}
+
+__extension__ extern __inline int32_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmlsdavaxq_p_s32 (int32_t __a, int32x4_t __b, int32x4_t __c, mve_pred16_t __p)
+{
+ return __builtin_mve_vmlsdavaxq_p_sv4si (__a, __b, __c, __p);
+}
+
+__extension__ extern __inline int32_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmlsdavaxq_p_s16 (int32_t __a, int16x8_t __b, int16x8_t __c, mve_pred16_t __p)
+{
+ return __builtin_mve_vmlsdavaxq_p_sv8hi (__a, __b, __c, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmulhq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vmulhq_m_sv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmulhq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vmulhq_m_sv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmulhq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vmulhq_m_sv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmulhq_m_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vmulhq_m_uv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmulhq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vmulhq_m_uv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmulhq_m_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vmulhq_m_uv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmullbq_int_m_s8 (int16x8_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vmullbq_int_m_sv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int64x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmullbq_int_m_s32 (int64x2_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vmullbq_int_m_sv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmullbq_int_m_s16 (int32x4_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vmullbq_int_m_sv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmullbq_int_m_u8 (uint16x8_t __inactive, uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vmullbq_int_m_uv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint64x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmullbq_int_m_u32 (uint64x2_t __inactive, uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vmullbq_int_m_uv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmullbq_int_m_u16 (uint32x4_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vmullbq_int_m_uv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmulltq_int_m_s8 (int16x8_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vmulltq_int_m_sv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int64x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmulltq_int_m_s32 (int64x2_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vmulltq_int_m_sv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmulltq_int_m_s16 (int32x4_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vmulltq_int_m_sv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmulltq_int_m_u8 (uint16x8_t __inactive, uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vmulltq_int_m_uv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint64x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmulltq_int_m_u32 (uint64x2_t __inactive, uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vmulltq_int_m_uv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmulltq_int_m_u16 (uint32x4_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vmulltq_int_m_uv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmulq_m_n_s8 (int8x16_t __inactive, int8x16_t __a, int8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vmulq_m_n_sv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmulq_m_n_s32 (int32x4_t __inactive, int32x4_t __a, int32_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vmulq_m_n_sv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmulq_m_n_s16 (int16x8_t __inactive, int16x8_t __a, int16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vmulq_m_n_sv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmulq_m_n_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vmulq_m_n_uv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmulq_m_n_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vmulq_m_n_uv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmulq_m_n_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vmulq_m_n_uv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmulq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vmulq_m_sv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmulq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vmulq_m_sv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmulq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vmulq_m_sv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmulq_m_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vmulq_m_uv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmulq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vmulq_m_uv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmulq_m_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vmulq_m_uv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vornq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vornq_m_sv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vornq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vornq_m_sv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vornq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vornq_m_sv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vornq_m_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vornq_m_uv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vornq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vornq_m_uv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vornq_m_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vornq_m_uv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vorrq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vorrq_m_sv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vorrq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vorrq_m_sv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vorrq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vorrq_m_sv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vorrq_m_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vorrq_m_uv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vorrq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vorrq_m_uv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vorrq_m_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vorrq_m_uv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqaddq_m_n_s8 (int8x16_t __inactive, int8x16_t __a, int8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqaddq_m_n_sv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqaddq_m_n_s32 (int32x4_t __inactive, int32x4_t __a, int32_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqaddq_m_n_sv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqaddq_m_n_s16 (int16x8_t __inactive, int16x8_t __a, int16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqaddq_m_n_sv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqaddq_m_n_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqaddq_m_n_uv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqaddq_m_n_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqaddq_m_n_uv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqaddq_m_n_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqaddq_m_n_uv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqaddq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqaddq_m_sv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqaddq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqaddq_m_sv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqaddq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqaddq_m_sv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqaddq_m_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqaddq_m_uv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqaddq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqaddq_m_uv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqaddq_m_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqaddq_m_uv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqdmladhq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqdmladhq_m_sv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqdmladhq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqdmladhq_m_sv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqdmladhq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqdmladhq_m_sv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqdmladhxq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqdmladhxq_m_sv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqdmladhxq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqdmladhxq_m_sv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqdmladhxq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqdmladhxq_m_sv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqdmlahq_m_n_s8 (int8x16_t __a, int8x16_t __b, int8_t __c, mve_pred16_t __p)
+{
+ return __builtin_mve_vqdmlahq_m_n_sv16qi (__a, __b, __c, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqdmlahq_m_n_s32 (int32x4_t __a, int32x4_t __b, int32_t __c, mve_pred16_t __p)
+{
+ return __builtin_mve_vqdmlahq_m_n_sv4si (__a, __b, __c, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqdmlahq_m_n_s16 (int16x8_t __a, int16x8_t __b, int16_t __c, mve_pred16_t __p)
+{
+ return __builtin_mve_vqdmlahq_m_n_sv8hi (__a, __b, __c, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqdmlsdhq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqdmlsdhq_m_sv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqdmlsdhq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqdmlsdhq_m_sv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqdmlsdhq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqdmlsdhq_m_sv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqdmlsdhxq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqdmlsdhxq_m_sv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqdmlsdhxq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqdmlsdhxq_m_sv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqdmlsdhxq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqdmlsdhxq_m_sv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqdmulhq_m_n_s8 (int8x16_t __inactive, int8x16_t __a, int8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqdmulhq_m_n_sv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqdmulhq_m_n_s32 (int32x4_t __inactive, int32x4_t __a, int32_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqdmulhq_m_n_sv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqdmulhq_m_n_s16 (int16x8_t __inactive, int16x8_t __a, int16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqdmulhq_m_n_sv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqdmulhq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqdmulhq_m_sv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqdmulhq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqdmulhq_m_sv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqdmulhq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqdmulhq_m_sv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqrdmladhq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqrdmladhq_m_sv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqrdmladhq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqrdmladhq_m_sv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqrdmladhq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqrdmladhq_m_sv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqrdmladhxq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqrdmladhxq_m_sv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqrdmladhxq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqrdmladhxq_m_sv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqrdmladhxq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqrdmladhxq_m_sv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqrdmlahq_m_n_s8 (int8x16_t __a, int8x16_t __b, int8_t __c, mve_pred16_t __p)
+{
+ return __builtin_mve_vqrdmlahq_m_n_sv16qi (__a, __b, __c, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqrdmlahq_m_n_s32 (int32x4_t __a, int32x4_t __b, int32_t __c, mve_pred16_t __p)
+{
+ return __builtin_mve_vqrdmlahq_m_n_sv4si (__a, __b, __c, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqrdmlahq_m_n_s16 (int16x8_t __a, int16x8_t __b, int16_t __c, mve_pred16_t __p)
+{
+ return __builtin_mve_vqrdmlahq_m_n_sv8hi (__a, __b, __c, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqrdmlashq_m_n_s8 (int8x16_t __a, int8x16_t __b, int8_t __c, mve_pred16_t __p)
+{
+ return __builtin_mve_vqrdmlashq_m_n_sv16qi (__a, __b, __c, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqrdmlashq_m_n_s32 (int32x4_t __a, int32x4_t __b, int32_t __c, mve_pred16_t __p)
+{
+ return __builtin_mve_vqrdmlashq_m_n_sv4si (__a, __b, __c, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqrdmlashq_m_n_s16 (int16x8_t __a, int16x8_t __b, int16_t __c, mve_pred16_t __p)
+{
+ return __builtin_mve_vqrdmlashq_m_n_sv8hi (__a, __b, __c, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqrdmlsdhq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqrdmlsdhq_m_sv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqrdmlsdhq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqrdmlsdhq_m_sv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqrdmlsdhq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqrdmlsdhq_m_sv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqrdmlsdhxq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqrdmlsdhxq_m_sv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqrdmlsdhxq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqrdmlsdhxq_m_sv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqrdmlsdhxq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqrdmlsdhxq_m_sv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqrdmulhq_m_n_s8 (int8x16_t __inactive, int8x16_t __a, int8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqrdmulhq_m_n_sv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqrdmulhq_m_n_s32 (int32x4_t __inactive, int32x4_t __a, int32_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqrdmulhq_m_n_sv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqrdmulhq_m_n_s16 (int16x8_t __inactive, int16x8_t __a, int16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqrdmulhq_m_n_sv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqrdmulhq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqrdmulhq_m_sv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqrdmulhq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqrdmulhq_m_sv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqrdmulhq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqrdmulhq_m_sv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqrshlq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqrshlq_m_sv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqrshlq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqrshlq_m_sv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqrshlq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqrshlq_m_sv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqrshlq_m_u8 (uint8x16_t __inactive, uint8x16_t __a, int8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqrshlq_m_uv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqrshlq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, int32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqrshlq_m_uv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqrshlq_m_u16 (uint16x8_t __inactive, uint16x8_t __a, int16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqrshlq_m_uv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqshlq_m_n_s8 (int8x16_t __inactive, int8x16_t __a, const int __imm, mve_pred16_t __p)
+{
+ return __builtin_mve_vqshlq_m_n_sv16qi (__inactive, __a, __imm, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqshlq_m_n_s32 (int32x4_t __inactive, int32x4_t __a, const int __imm, mve_pred16_t __p)
+{
+ return __builtin_mve_vqshlq_m_n_sv4si (__inactive, __a, __imm, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqshlq_m_n_s16 (int16x8_t __inactive, int16x8_t __a, const int __imm, mve_pred16_t __p)
+{
+ return __builtin_mve_vqshlq_m_n_sv8hi (__inactive, __a, __imm, __p);
+}
+
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqshlq_m_n_u8 (uint8x16_t __inactive, uint8x16_t __a, const int __imm, mve_pred16_t __p)
+{
+ return __builtin_mve_vqshlq_m_n_uv16qi (__inactive, __a, __imm, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqshlq_m_n_u32 (uint32x4_t __inactive, uint32x4_t __a, const int __imm, mve_pred16_t __p)
+{
+ return __builtin_mve_vqshlq_m_n_uv4si (__inactive, __a, __imm, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqshlq_m_n_u16 (uint16x8_t __inactive, uint16x8_t __a, const int __imm, mve_pred16_t __p)
+{
+ return __builtin_mve_vqshlq_m_n_uv8hi (__inactive, __a, __imm, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqshlq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqshlq_m_sv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqshlq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqshlq_m_sv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqshlq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqshlq_m_sv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqshlq_m_u8 (uint8x16_t __inactive, uint8x16_t __a, int8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqshlq_m_uv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqshlq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, int32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqshlq_m_uv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqshlq_m_u16 (uint16x8_t __inactive, uint16x8_t __a, int16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqshlq_m_uv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqsubq_m_n_s8 (int8x16_t __inactive, int8x16_t __a, int8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqsubq_m_n_sv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqsubq_m_n_s32 (int32x4_t __inactive, int32x4_t __a, int32_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqsubq_m_n_sv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqsubq_m_n_s16 (int16x8_t __inactive, int16x8_t __a, int16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqsubq_m_n_sv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqsubq_m_n_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqsubq_m_n_uv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqsubq_m_n_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqsubq_m_n_uv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqsubq_m_n_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqsubq_m_n_uv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqsubq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqsubq_m_sv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqsubq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqsubq_m_sv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqsubq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqsubq_m_sv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqsubq_m_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqsubq_m_uv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqsubq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqsubq_m_uv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vqsubq_m_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vqsubq_m_uv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrhaddq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vrhaddq_m_sv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrhaddq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vrhaddq_m_sv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrhaddq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vrhaddq_m_sv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrhaddq_m_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vrhaddq_m_uv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrhaddq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vrhaddq_m_uv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrhaddq_m_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vrhaddq_m_uv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrmulhq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vrmulhq_m_sv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrmulhq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vrmulhq_m_sv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrmulhq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vrmulhq_m_sv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrmulhq_m_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vrmulhq_m_uv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrmulhq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vrmulhq_m_uv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrmulhq_m_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vrmulhq_m_uv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrshlq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vrshlq_m_sv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrshlq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vrshlq_m_sv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrshlq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vrshlq_m_sv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrshlq_m_u8 (uint8x16_t __inactive, uint8x16_t __a, int8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vrshlq_m_uv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrshlq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, int32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vrshlq_m_uv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrshlq_m_u16 (uint16x8_t __inactive, uint16x8_t __a, int16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vrshlq_m_uv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrshrq_m_n_s8 (int8x16_t __inactive, int8x16_t __a, const int __imm, mve_pred16_t __p)
+{
+ return __builtin_mve_vrshrq_m_n_sv16qi (__inactive, __a, __imm, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrshrq_m_n_s32 (int32x4_t __inactive, int32x4_t __a, const int __imm, mve_pred16_t __p)
+{
+ return __builtin_mve_vrshrq_m_n_sv4si (__inactive, __a, __imm, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrshrq_m_n_s16 (int16x8_t __inactive, int16x8_t __a, const int __imm, mve_pred16_t __p)
+{
+ return __builtin_mve_vrshrq_m_n_sv8hi (__inactive, __a, __imm, __p);
+}
+
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrshrq_m_n_u8 (uint8x16_t __inactive, uint8x16_t __a, const int __imm, mve_pred16_t __p)
+{
+ return __builtin_mve_vrshrq_m_n_uv16qi (__inactive, __a, __imm, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrshrq_m_n_u32 (uint32x4_t __inactive, uint32x4_t __a, const int __imm, mve_pred16_t __p)
+{
+ return __builtin_mve_vrshrq_m_n_uv4si (__inactive, __a, __imm, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrshrq_m_n_u16 (uint16x8_t __inactive, uint16x8_t __a, const int __imm, mve_pred16_t __p)
+{
+ return __builtin_mve_vrshrq_m_n_uv8hi (__inactive, __a, __imm, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vshlq_m_n_s8 (int8x16_t __inactive, int8x16_t __a, const int __imm, mve_pred16_t __p)
+{
+ return __builtin_mve_vshlq_m_n_sv16qi (__inactive, __a, __imm, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vshlq_m_n_s32 (int32x4_t __inactive, int32x4_t __a, const int __imm, mve_pred16_t __p)
+{
+ return __builtin_mve_vshlq_m_n_sv4si (__inactive, __a, __imm, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vshlq_m_n_s16 (int16x8_t __inactive, int16x8_t __a, const int __imm, mve_pred16_t __p)
+{
+ return __builtin_mve_vshlq_m_n_sv8hi (__inactive, __a, __imm, __p);
+}
+
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vshlq_m_n_u8 (uint8x16_t __inactive, uint8x16_t __a, const int __imm, mve_pred16_t __p)
+{
+ return __builtin_mve_vshlq_m_n_uv16qi (__inactive, __a, __imm, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vshlq_m_n_u32 (uint32x4_t __inactive, uint32x4_t __a, const int __imm, mve_pred16_t __p)
+{
+ return __builtin_mve_vshlq_m_n_uv4si (__inactive, __a, __imm, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vshlq_m_n_u16 (uint16x8_t __inactive, uint16x8_t __a, const int __imm, mve_pred16_t __p)
+{
+ return __builtin_mve_vshlq_m_n_uv8hi (__inactive, __a, __imm, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vshrq_m_n_s8 (int8x16_t __inactive, int8x16_t __a, const int __imm, mve_pred16_t __p)
+{
+ return __builtin_mve_vshrq_m_n_sv16qi (__inactive, __a, __imm, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vshrq_m_n_s32 (int32x4_t __inactive, int32x4_t __a, const int __imm, mve_pred16_t __p)
+{
+ return __builtin_mve_vshrq_m_n_sv4si (__inactive, __a, __imm, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vshrq_m_n_s16 (int16x8_t __inactive, int16x8_t __a, const int __imm, mve_pred16_t __p)
+{
+ return __builtin_mve_vshrq_m_n_sv8hi (__inactive, __a, __imm, __p);
+}
+
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vshrq_m_n_u8 (uint8x16_t __inactive, uint8x16_t __a, const int __imm, mve_pred16_t __p)
+{
+ return __builtin_mve_vshrq_m_n_uv16qi (__inactive, __a, __imm, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vshrq_m_n_u32 (uint32x4_t __inactive, uint32x4_t __a, const int __imm, mve_pred16_t __p)
+{
+ return __builtin_mve_vshrq_m_n_uv4si (__inactive, __a, __imm, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vshrq_m_n_u16 (uint16x8_t __inactive, uint16x8_t __a, const int __imm, mve_pred16_t __p)
+{
+ return __builtin_mve_vshrq_m_n_uv8hi (__inactive, __a, __imm, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vsliq_m_n_s8 (int8x16_t __a, int8x16_t __b, const int __imm, mve_pred16_t __p)
+{
+ return __builtin_mve_vsliq_m_n_sv16qi (__a, __b, __imm, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vsliq_m_n_s32 (int32x4_t __a, int32x4_t __b, const int __imm, mve_pred16_t __p)
+{
+ return __builtin_mve_vsliq_m_n_sv4si (__a, __b, __imm, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vsliq_m_n_s16 (int16x8_t __a, int16x8_t __b, const int __imm, mve_pred16_t __p)
+{
+ return __builtin_mve_vsliq_m_n_sv8hi (__a, __b, __imm, __p);
+}
+
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vsliq_m_n_u8 (uint8x16_t __a, uint8x16_t __b, const int __imm, mve_pred16_t __p)
+{
+ return __builtin_mve_vsliq_m_n_uv16qi (__a, __b, __imm, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vsliq_m_n_u32 (uint32x4_t __a, uint32x4_t __b, const int __imm, mve_pred16_t __p)
+{
+ return __builtin_mve_vsliq_m_n_uv4si (__a, __b, __imm, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vsliq_m_n_u16 (uint16x8_t __a, uint16x8_t __b, const int __imm, mve_pred16_t __p)
+{
+ return __builtin_mve_vsliq_m_n_uv8hi (__a, __b, __imm, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vsubq_m_n_s8 (int8x16_t __inactive, int8x16_t __a, int8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vsubq_m_n_sv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vsubq_m_n_s32 (int32x4_t __inactive, int32x4_t __a, int32_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vsubq_m_n_sv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vsubq_m_n_s16 (int16x8_t __inactive, int16x8_t __a, int16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vsubq_m_n_sv8hi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vsubq_m_n_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vsubq_m_n_uv16qi (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vsubq_m_n_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vsubq_m_n_uv4si (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vsubq_m_n_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vsubq_m_n_uv8hi (__inactive, __a, __b, __p);
+}
+
#if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */
__extension__ extern __inline void
@@ -13637,6 +16037,12 @@ extern void *__ARM_undef;
__typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \
int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsubq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsubq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsubq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
@@ -13656,8 +16062,593 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vabavq_p_u16(__p0, __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vabavq_p_u32(__p0, __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+#define vabdq_m(p0,p1,p2,p3) __arm_vabdq_m(p0,p1,p2,p3)
+#define __arm_vabdq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
+ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vabdq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vabdq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vabdq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vabdq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vabdq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vabdq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+
+#define vandq_m(p0,p1,p2,p3) __arm_vandq_m(p0,p1,p2,p3)
+#define __arm_vandq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
+ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vandq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vandq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vandq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vandq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vandq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vandq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+
+#define vbicq_m(p0,p1,p2,p3) __arm_vbicq_m(p0,p1,p2,p3)
+#define __arm_vbicq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
+ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vbicq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vbicq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vbicq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vbicq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vbicq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vbicq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+
+#define vbrsrq_m(p0,p1,p2,p3) __arm_vbrsrq_m(p0,p1,p2,p3)
+#define __arm_vbrsrq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
+ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vbrsrq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __p2, p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vbrsrq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __p2, p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vbrsrq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __p2, p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vbrsrq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __p2, p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vbrsrq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __p2, p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vbrsrq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __p2, p3));})
+
+#define vcaddq_rot270_m(p0,p1,p2,p3) __arm_vcaddq_rot270_m(p0,p1,p2,p3)
+#define __arm_vcaddq_rot270_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
+ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcaddq_rot270_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcaddq_rot270_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcaddq_rot270_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcaddq_rot270_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcaddq_rot270_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcaddq_rot270_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+
+#define vcaddq_rot90_m(p0,p1,p2,p3) __arm_vcaddq_rot90_m(p0,p1,p2,p3)
+#define __arm_vcaddq_rot90_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
+ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcaddq_rot90_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcaddq_rot90_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcaddq_rot90_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcaddq_rot90_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcaddq_rot90_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcaddq_rot90_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+
+#define veorq_m(p0,p1,p2,p3) __arm_veorq_m(p0,p1,p2,p3)
+#define __arm_veorq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
+ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_veorq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_veorq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_veorq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_veorq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_veorq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_veorq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+
+#define vmaxq_m(p0,p1,p2,p3) __arm_vmaxq_m(p0,p1,p2,p3)
+#define __arm_vmaxq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
+ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmaxq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmaxq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmaxq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmaxq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmaxq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmaxq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+
+#define vminq_m(p0,p1,p2,p3) __arm_vminq_m(p0,p1,p2,p3)
+#define __arm_vminq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
+ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vminq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vminq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vminq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vminq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vminq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vminq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+
+#define vmladavaq_p(p0,p1,p2,p3) __arm_vmladavaq_p(p0,p1,p2,p3)
+#define __arm_vmladavaq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
+ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int32_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaq_p_s8 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int32_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaq_p_s16 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaq_p_s32 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint32_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaq_p_u8 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint32_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaq_p_u16 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint32_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaq_p_u32 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+
+#define vmlaq_m(p0,p1,p2,p3) __arm_vmlaq_m(p0,p1,p2,p3)
+#define __arm_vmlaq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
+ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vmlaq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vmlaq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vmlaq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vmlaq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vmlaq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vmlaq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3));})
+
+#define vmlasq_m(p0,p1,p2,p3) __arm_vmlasq_m(p0,p1,p2,p3)
+#define __arm_vmlasq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
+ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vmlasq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vmlasq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vmlasq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vmlasq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vmlasq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vmlasq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3));})
+
+#define vmulhq_m(p0,p1,p2,p3) __arm_vmulhq_m(p0,p1,p2,p3)
+#define __arm_vmulhq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
+ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulhq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulhq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulhq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulhq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulhq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmulhq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+
+#define vmullbq_int_m(p0,p1,p2,p3) __arm_vmullbq_int_m(p0,p1,p2,p3)
+#define __arm_vmullbq_int_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
+ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmullbq_int_m_s8 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmullbq_int_m_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmullbq_int_m_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmullbq_int_m_u8 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmullbq_int_m_u16 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint64x2_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmullbq_int_m_u32 (__ARM_mve_coerce(__p0, uint64x2_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+
+#define vmulltq_int_m(p0,p1,p2,p3) __arm_vmulltq_int_m(p0,p1,p2,p3)
+#define __arm_vmulltq_int_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
+ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulltq_int_m_s8 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulltq_int_m_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulltq_int_m_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulltq_int_m_u8 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulltq_int_m_u16 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint64x2_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmulltq_int_m_u32 (__ARM_mve_coerce(__p0, uint64x2_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+
+#define vornq_m(p0,p1,p2,p3) __arm_vornq_m(p0,p1,p2,p3)
+#define __arm_vornq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
+ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vornq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vornq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vornq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vornq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vornq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vornq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+
+#define vorrq_m(p0,p1,p2,p3) __arm_vorrq_m(p0,p1,p2,p3)
+#define __arm_vorrq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
+ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vorrq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vorrq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vorrq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vorrq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vorrq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vorrq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+
+#define vqdmlahq_m(p0,p1,p2,p3) __arm_vqdmlahq_m(p0,p1,p2,p3)
+#define __arm_vqdmlahq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
+ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vqdmlahq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqdmlahq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqdmlahq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3));})
+
+#define vqrdmlahq_m(p0,p1,p2,p3) __arm_vqrdmlahq_m(p0,p1,p2,p3)
+#define __arm_vqrdmlahq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
+ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vqrdmlahq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqrdmlahq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqrdmlahq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3));})
+
+#define vqrdmlashq_m(p0,p1,p2,p3) __arm_vqrdmlashq_m(p0,p1,p2,p3)
+#define __arm_vqrdmlashq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
+ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vqrdmlashq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqrdmlashq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqrdmlashq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3));})
+
+#define vqrshlq_m(p0,p1,p2,p3) __arm_vqrshlq_m(p0,p1,p2,p3)
+#define __arm_vqrshlq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
+ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrshlq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrshlq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrshlq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrshlq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrshlq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrshlq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));})
+
+#define vqshlq_m_n(p0,p1,p2,p3) __arm_vqshlq_m_n(p0,p1,p2,p3)
+#define __arm_vqshlq_m_n(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
+ __typeof(p1) __p1 = (p1); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqshlq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2, p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqshlq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqshlq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vqshlq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2, p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vqshlq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vqshlq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2, p3));})
+
+#define vqshlq_m(p0,p1,p2,p3) __arm_vqshlq_m(p0,p1,p2,p3)
+#define __arm_vqshlq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
+ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqshlq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqshlq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqshlq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqshlq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqshlq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqshlq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));})
+
+#define vrhaddq_m(p0,p1,p2,p3) __arm_vrhaddq_m(p0,p1,p2,p3)
+#define __arm_vrhaddq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
+ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrhaddq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrhaddq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrhaddq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vrhaddq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vrhaddq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrhaddq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+
+#define vrmulhq_m(p0,p1,p2,p3) __arm_vrmulhq_m(p0,p1,p2,p3)
+#define __arm_vrmulhq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
+ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrmulhq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrmulhq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrmulhq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vrmulhq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vrmulhq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrmulhq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+
+#define vrshlq_m(p0,p1,p2,p3) __arm_vrshlq_m(p0,p1,p2,p3)
+#define __arm_vrshlq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
+ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrshlq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrshlq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrshlq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrshlq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrshlq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrshlq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));})
+
+#define vrshrq_m(p0,p1,p2,p3) __arm_vrshrq_m(p0,p1,p2,p3)
+#define __arm_vrshrq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
+ __typeof(p1) __p1 = (p1); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrshrq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2, p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrshrq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrshrq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vrshrq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2, p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vrshrq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrshrq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2, p3));})
+
+#define vshrq_m(p0,p1,p2,p3) __arm_vshrq_m(p0,p1,p2,p3)
+#define __arm_vshrq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
+ __typeof(p1) __p1 = (p1); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vshrq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2, p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vshrq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vshrq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vshrq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2, p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vshrq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vshrq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2, p3));})
+
+#define vsliq_m(p0,p1,p2,p3) __arm_vsliq_m(p0,p1,p2,p3)
+#define __arm_vsliq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
+ __typeof(p1) __p1 = (p1); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsliq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2, p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsliq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsliq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vsliq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2, p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vsliq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsliq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2, p3));})
+
+#define vaddq_m(p0,p1,p2,p3) __arm_vaddq_m(p0,p1,p2,p3)
+#define __arm_vaddq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
+ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vaddq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vaddq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vaddq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vaddq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vaddq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vaddq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+
+#define vhaddq_m(p0,p1,p2,p3) __arm_vhaddq_m(p0,p1,p2,p3)
+#define __arm_vhaddq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
+ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vhaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vhaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vhaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vhaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vhaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vhaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhaddq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhaddq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhaddq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vhaddq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vhaddq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vhaddq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+
+#define vhcaddq_rot270_m(p0,p1,p2,p3) __arm_vhcaddq_rot270_m(p0,p1,p2,p3)
+#define __arm_vhcaddq_rot270_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
+ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhcaddq_rot270_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhcaddq_rot270_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhcaddq_rot270_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));})
+
+#define vhcaddq_rot90_m(p0,p1,p2,p3) __arm_vhcaddq_rot90_m(p0,p1,p2,p3)
+#define __arm_vhcaddq_rot90_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
+ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhcaddq_rot90_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhcaddq_rot90_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhcaddq_rot90_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));})
+
+#define vhsubq_m(p0,p1,p2,p3) __arm_vhsubq_m(p0,p1,p2,p3)
+#define __arm_vhsubq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
+ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhsubq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhsubq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhsubq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vhsubq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vhsubq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vhsubq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vhsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vhsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vhsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vhsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vhsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vhsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3));})
+
+#define vmulq_m(p0,p1,p2,p3) __arm_vmulq_m(p0,p1,p2,p3)
+#define __arm_vmulq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
+ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vmulq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vmulq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vmulq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vmulq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vmulq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vmulq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmulq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+
+#define vqaddq_m(p0,p1,p2,p3) __arm_vqaddq_m(p0,p1,p2,p3)
+#define __arm_vqaddq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
+ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vqaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vqaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vqaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vqaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqaddq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqaddq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqaddq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vqaddq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vqaddq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vqaddq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+
+#define vqdmulhq_m(p0,p1,p2,p3) __arm_vqdmulhq_m(p0,p1,p2,p3)
+#define __arm_vqdmulhq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
+ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vqdmulhq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqdmulhq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqdmulhq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmulhq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulhq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulhq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));})
+
+#define vqsubq_m(p0,p1,p2,p3) __arm_vqsubq_m(p0,p1,p2,p3)
+#define __arm_vqsubq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
+ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vqsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vqsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vqsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vqsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqsubq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqsubq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqsubq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vqsubq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vqsubq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vqsubq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+
+#define vqrdmulhq_m(p0,p1,p2,p3) __arm_vqrdmulhq_m(p0,p1,p2,p3)
+#define __arm_vqrdmulhq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
+ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmulhq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmulhq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmulhq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vqrdmulhq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vqrdmulhq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vqrdmulhq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3));})
+
+
+#define vqrdmlsdhxq_m(p0,p1,p2,p3) __arm_vqrdmlsdhxq_m(p0,p1,p2,p3)
+#define __arm_vqrdmlsdhxq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
+ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmlsdhxq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmlsdhxq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmlsdhxq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));})
+
+#define vqrdmlsdhq_m(p0,p1,p2,p3) __arm_vqrdmlsdhq_m(p0,p1,p2,p3)
+#define __arm_vqrdmlsdhq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
+ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmlsdhq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmlsdhq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmlsdhq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));})
+
+#define vqrdmladhq_m(p0,p1,p2,p3) __arm_vqrdmladhq_m(p0,p1,p2,p3)
+#define __arm_vqrdmladhq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
+ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmladhq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmladhq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmladhq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));})
+
+#define vqrdmladhxq_m(p0,p1,p2,p3) __arm_vqrdmladhxq_m(p0,p1,p2,p3)
+#define __arm_vqrdmladhxq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
+ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmladhxq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmladhxq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmladhxq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));})
+
+#define vmlsdavaxq_p(p0,p1,p2,p3) __arm_vmlsdavaxq_p(p0,p1,p2,p3)
+#define __arm_vmlsdavaxq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
+ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmlsdavaxq_p_s8 (__p0, __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlsdavaxq_p_s16 (__p0, __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlsdavaxq_p_s32 (__p0, __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));})
+
+#define vmlsdavaq_p(p0,p1,p2,p3) __arm_vmlsdavaq_p(p0,p1,p2,p3)
+#define __arm_vmlsdavaq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
+ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmlsdavaq_p_s8(__p0, __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlsdavaq_p_s16(__p0, __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlsdavaq_p_s32(__p0, __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));})
+
+#define vmladavaxq_p(p0,p1,p2,p3) __arm_vmladavaxq_p(p0,p1,p2,p3)
+#define __arm_vmladavaxq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
+ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int32_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaxq_p_s8 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int32_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaxq_p_s16 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaxq_p_s32 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));})
+
#endif /* MVE Integer. */
+#define vqdmladhq_m(p0,p1,p2,p3) __arm_vqdmladhq_m(p0,p1,p2,p3)
+#define __arm_vqdmladhq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
+ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmladhq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmladhq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmladhq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));})
+
+#define vqdmladhxq_m(p0,p1,p2,p3) __arm_vqdmladhxq_m(p0,p1,p2,p3)
+#define __arm_vqdmladhxq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
+ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmladhxq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmladhxq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmladhxq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));})
+
+#define vqdmlsdhq_m(p0,p1,p2,p3) __arm_vqdmlsdhq_m(p0,p1,p2,p3)
+#define __arm_vqdmlsdhq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
+ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmlsdhq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmlsdhq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmlsdhq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));})
+
+#define vqdmlsdhxq_m(p0,p1,p2,p3) __arm_vqdmlsdhxq_m(p0,p1,p2,p3)
+#define __arm_vqdmlsdhxq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
+ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmlsdhxq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmlsdhxq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmlsdhxq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));})
+
#define vqabsq_m(p0,p1,p2) __arm_vqabsq_m(p0,p1,p2)
#define __arm_vqabsq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
@@ -13716,6 +16707,27 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vshlq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vshlq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));})
+#define vshlq_m_n(p0,p1,p2,p3) __arm_vshlq_m_n(p0,p1,p2,p3)
+#define __arm_vshlq_m_n(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
+ __typeof(p1) __p1 = (p1); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vshlq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2, p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vshlq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vshlq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vshlq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2, p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vshlq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vshlq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2, p3));})
+
+#define vshlq_m_r(p0,p1,p2) __arm_vshlq_m_r(p0,p1,p2)
+#define __arm_vshlq_m_r(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
+ int (*)[__ARM_mve_type_int8x16_t]: __arm_vshlq_m_r_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1, p2), \
+ int (*)[__ARM_mve_type_int16x8_t]: __arm_vshlq_m_r_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1, p2), \
+ int (*)[__ARM_mve_type_int32x4_t]: __arm_vshlq_m_r_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1, p2), \
+ int (*)[__ARM_mve_type_uint8x16_t]: __arm_vshlq_m_r_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1, p2), \
+ int (*)[__ARM_mve_type_uint16x8_t]: __arm_vshlq_m_r_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1, p2), \
+ int (*)[__ARM_mve_type_uint32x4_t]: __arm_vshlq_m_r_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1, p2));})
+
#define vsriq_m(p0,p1,p2,p3) __arm_vsriq_m(p0,p1,p2,p3)
#define __arm_vsriq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def
index c7d64ff7858..666558899a9 100644
--- a/gcc/config/arm/arm_mve_builtins.def
+++ b/gcc/config/arm/arm_mve_builtins.def
@@ -513,3 +513,103 @@ VAR3 (QUADOP_UNONE_UNONE_NONE_NONE_UNONE, vabavq_p_s, v16qi, v8hi, v4si)
VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vabavq_p_u, v16qi, v8hi, v4si)
VAR3 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE, vshlq_m_u, v16qi, v8hi, v4si)
VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vshlq_m_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vsubq_m_n_u, v16qi, v8hi, v4si)
+VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vrmulhq_m_u, v16qi, v8hi, v4si)
+VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vrhaddq_m_u, v16qi, v8hi, v4si)
+VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vqsubq_m_u, v16qi, v8hi, v4si)
+VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vqsubq_m_n_u, v16qi, v8hi, v4si)
+VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vqaddq_m_u, v16qi, v8hi, v4si)
+VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vqaddq_m_n_u, v16qi, v8hi, v4si)
+VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vorrq_m_u, v16qi, v8hi, v4si)
+VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vornq_m_u, v16qi, v8hi, v4si)
+VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vmulq_m_u, v16qi, v8hi, v4si)
+VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vmulq_m_n_u, v16qi, v8hi, v4si)
+VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vmulltq_int_m_u, v16qi, v8hi, v4si)
+VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vmullbq_int_m_u, v16qi, v8hi, v4si)
+VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vmulhq_m_u, v16qi, v8hi, v4si)
+VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vmlasq_m_n_u, v16qi, v8hi, v4si)
+VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vmlaq_m_n_u, v16qi, v8hi, v4si)
+VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vmladavaq_p_u, v16qi, v8hi, v4si)
+VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vminq_m_u, v16qi, v8hi, v4si)
+VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vmaxq_m_u, v16qi, v8hi, v4si)
+VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vhsubq_m_u, v16qi, v8hi, v4si)
+VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vhsubq_m_n_u, v16qi, v8hi, v4si)
+VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vhaddq_m_u, v16qi, v8hi, v4si)
+VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vhaddq_m_n_u, v16qi, v8hi, v4si)
+VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, veorq_m_u, v16qi, v8hi, v4si)
+VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vcaddq_rot90_m_u, v16qi, v8hi, v4si)
+VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vcaddq_rot270_m_u, v16qi, v8hi, v4si)
+VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vbicq_m_u, v16qi, v8hi, v4si)
+VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vandq_m_u, v16qi, v8hi, v4si)
+VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vaddq_m_u, v16qi, v8hi, v4si)
+VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vaddq_m_n_u, v16qi, v8hi, v4si)
+VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vabdq_m_u, v16qi, v8hi, v4si)
+VAR3 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE, vrshlq_m_u, v16qi, v8hi, v4si)
+VAR3 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE, vqshlq_m_u, v16qi, v8hi, v4si)
+VAR3 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE, vqrshlq_m_u, v16qi, v8hi, v4si)
+VAR3 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE, vbrsrq_m_n_u, v16qi, v8hi, v4si)
+VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vsliq_m_n_u, v16qi, v8hi, v4si)
+VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vshrq_m_n_u, v16qi, v8hi, v4si)
+VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vshlq_m_n_u, v16qi, v8hi, v4si)
+VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vrshrq_m_n_u, v16qi, v8hi, v4si)
+VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vqshlq_m_n_u, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vsubq_m_n_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vrshlq_m_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vrmulhq_m_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vrhaddq_m_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqsubq_m_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqsubq_m_n_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqshlq_m_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqrshlq_m_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqrdmulhq_m_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqrdmulhq_m_n_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqrdmlsdhxq_m_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqrdmlsdhq_m_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqrdmlashq_m_n_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqrdmlahq_m_n_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqrdmladhxq_m_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqrdmladhq_m_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqdmulhq_m_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqdmulhq_m_n_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqdmlsdhxq_m_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqdmlsdhq_m_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqdmlahq_m_n_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqdmladhxq_m_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqdmladhq_m_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqaddq_m_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqaddq_m_n_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vorrq_m_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vornq_m_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmulq_m_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmulq_m_n_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmulltq_int_m_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmullbq_int_m_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmulhq_m_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmlsdavaxq_p_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmlsdavaq_p_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmlasq_m_n_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmlaq_m_n_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmladavaxq_p_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmladavaq_p_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vminq_m_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmaxq_m_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vhsubq_m_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vhsubq_m_n_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vhcaddq_rot90_m_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vhcaddq_rot270_m_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vhaddq_m_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vhaddq_m_n_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, veorq_m_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vcaddq_rot90_m_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vcaddq_rot270_m_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vbrsrq_m_n_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vbicq_m_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vandq_m_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vaddq_m_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vaddq_m_n_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vabdq_m_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vsliq_m_n_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vshrq_m_n_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vshlq_m_n_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vrshrq_m_n_s, v16qi, v8hi, v4si)
+VAR3 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vqshlq_m_n_s, v16qi, v8hi, v4si)
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index b65849cc54a..254cf93c11f 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -143,7 +143,37 @@
VCVTQ_M_N_FROM_F_U VQSHLUQ_M_N_S VABAVQ_P_S
VABAVQ_P_U VSHLQ_M_S VSHLQ_M_U VSRIQ_M_N_S
VSRIQ_M_N_U VSUBQ_M_U VSUBQ_M_S VCVTQ_M_N_TO_F_U
- VCVTQ_M_N_TO_F_S])
+ VCVTQ_M_N_TO_F_S VQADDQ_M_U VQADDQ_M_S
+ VRSHRQ_M_N_S VSUBQ_M_N_S VSUBQ_M_N_U VBRSRQ_M_N_S
+ VSUBQ_M_N_F VBICQ_M_F VHADDQ_M_U VBICQ_M_U VBICQ_M_S
+ VMULQ_M_N_U VHADDQ_M_S VORNQ_M_F VMLAQ_M_N_S VQSUBQ_M_U
+ VQSUBQ_M_S VMLAQ_M_N_U VQSUBQ_M_N_U VQSUBQ_M_N_S
+ VMULLTQ_INT_M_S VMULLTQ_INT_M_U VMULQ_M_N_S VMULQ_M_N_F
+ VMLASQ_M_N_U VMLASQ_M_N_S VMAXQ_M_U VQRDMLAHQ_M_N_U
+ VCADDQ_ROT270_M_F VCADDQ_ROT270_M_U VCADDQ_ROT270_M_S
+ VQRSHLQ_M_S VMULQ_M_F VRHADDQ_M_U VSHRQ_M_N_U
+ VRHADDQ_M_S VMULQ_M_S VMULQ_M_U VQRDMLASHQ_M_N_S
+ VRSHLQ_M_S VRSHLQ_M_U VRSHRQ_M_N_U VADDQ_M_N_F
+ VADDQ_M_N_S VADDQ_M_N_U VQRDMLASHQ_M_N_U VMAXQ_M_S
+ VQRDMLAHQ_M_N_S VORRQ_M_S VORRQ_M_U VORRQ_M_F
+ VQRSHLQ_M_U VRMULHQ_M_U VRMULHQ_M_S VMINQ_M_S VMINQ_M_U
+ VANDQ_M_F VANDQ_M_U VANDQ_M_S VHSUBQ_M_N_S VHSUBQ_M_N_U
+ VMULHQ_M_S VMULHQ_M_U VMULLBQ_INT_M_U
+ VMULLBQ_INT_M_S VCADDQ_ROT90_M_F
+ VSHRQ_M_N_S VADDQ_M_U VSLIQ_M_N_U
+ VQADDQ_M_N_S VBRSRQ_M_N_F VABDQ_M_F VBRSRQ_M_N_U
+ VEORQ_M_F VSHLQ_M_N_S VQDMLAHQ_M_N_U VQDMLAHQ_M_N_S
+ VSHLQ_M_N_U VMLADAVAQ_P_U VMLADAVAQ_P_S VSLIQ_M_N_S
+ VQSHLQ_M_U VQSHLQ_M_S VCADDQ_ROT90_M_U VCADDQ_ROT90_M_S
+ VORNQ_M_U VORNQ_M_S VQSHLQ_M_N_S VQSHLQ_M_N_U VADDQ_M_S
+ VHADDQ_M_N_S VADDQ_M_F VQADDQ_M_N_U VEORQ_M_S VEORQ_M_U
+ VHSUBQ_M_S VHSUBQ_M_U VHADDQ_M_N_U VHCADDQ_ROT90_M_S
+ VQRDMLSDHQ_M_S VQRDMLSDHXQ_M_S VQRDMLADHXQ_M_S
+ VQDMULHQ_M_S VMLADAVAXQ_P_S VQDMLADHXQ_M_S
+ VQRDMULHQ_M_S VMLSDAVAXQ_P_S VQDMULHQ_M_N_S
+ VHCADDQ_ROT270_M_S VQDMLSDHQ_M_S VQDMLSDHXQ_M_S
+ VMLSDAVAQ_P_S VQRDMLADHQ_M_S VQDMLADHQ_M_S
+ VQRDMULHQ_M_N_S])
(define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF")
(V8HF "V8HI") (V4SF "V4SI")])
@@ -251,7 +281,37 @@
(VABAVQ_P_S "s") (VSHLQ_M_S "s") (VSHLQ_M_U "u")
(VSRIQ_M_N_S "s") (VSRIQ_M_N_U "u") (VSUBQ_M_S "s")
(VSUBQ_M_U "u") (VCVTQ_M_N_TO_F_S "s")
- (VCVTQ_M_N_TO_F_U "u")])
+ (VCVTQ_M_N_TO_F_U "u") (VADDQ_M_N_U "u")
+ (VSHLQ_M_N_S "s") (VMAXQ_M_U "u") (VHSUBQ_M_N_U "u")
+ (VMULQ_M_N_S "s") (VQSHLQ_M_U "u") (VRHADDQ_M_S "s")
+ (VEORQ_M_U "u") (VSHRQ_M_N_U "u") (VCADDQ_ROT90_M_U "u")
+ (VMLADAVAQ_P_U "u") (VEORQ_M_S "s") (VBRSRQ_M_N_S "s")
+ (VMULQ_M_U "u") (VQRDMLAHQ_M_N_S "s") (VHSUBQ_M_N_S "s")
+ (VQRSHLQ_M_S "s") (VMULQ_M_N_U "u")
+ (VMULQ_M_S "s") (VQSHLQ_M_N_U "u") (VSLIQ_M_N_U "u")
+ (VMLADAVAQ_P_S "s") (VQRSHLQ_M_U "u")
+ (VMULLBQ_INT_M_U "u") (VSHLQ_M_N_U "u") (VQSUBQ_M_U "u")
+ (VQRDMLASHQ_M_N_U "u") (VRSHRQ_M_N_S "s")
+ (VORNQ_M_S "s") (VCADDQ_ROT270_M_S "s") (VRHADDQ_M_U "u")
+ (VRSHRQ_M_N_U "u") (VMLASQ_M_N_U "u") (VHSUBQ_M_U "u")
+ (VQSUBQ_M_N_S "s") (VMULLTQ_INT_M_S "s")
+ (VORRQ_M_S "s") (VQDMLAHQ_M_N_U "u") (VRSHLQ_M_S "s")
+ (VHADDQ_M_U "u") (VHADDQ_M_N_S "s") (VMULLTQ_INT_M_U "u")
+ (VORRQ_M_U "u") (VHADDQ_M_S "s") (VHADDQ_M_N_U "u")
+ (VQDMLAHQ_M_N_S "s") (VMAXQ_M_S "s") (VORNQ_M_U "u")
+ (VCADDQ_ROT270_M_U "u") (VQADDQ_M_U "u")
+ (VQRDMLASHQ_M_N_S "s") (VBICQ_M_U "u") (VMINQ_M_U "u")
+ (VSUBQ_M_N_S "s") (VMULLBQ_INT_M_S "s") (VQSUBQ_M_S "s")
+ (VCADDQ_ROT90_M_S "s") (VRMULHQ_M_S "s") (VANDQ_M_U "u")
+ (VMULHQ_M_S "s") (VADDQ_M_S "s") (VQRDMLAHQ_M_N_U "u")
+ (VMLASQ_M_N_S "s") (VHSUBQ_M_S "s") (VRMULHQ_M_U "u")
+ (VQADDQ_M_N_S "s") (VSHRQ_M_N_S "s") (VANDQ_M_S "s")
+ (VABDQ_M_U "u") (VQSHLQ_M_S "s") (VABDQ_M_S "s")
+ (VSUBQ_M_N_U "u") (VMLAQ_M_N_S "s") (VBRSRQ_M_N_U "u")
+ (VADDQ_M_U "u") (VRSHLQ_M_U "u") (VSLIQ_M_N_S "s")
+ (VQADDQ_M_N_U "u") (VADDQ_M_N_S "s") (VQSUBQ_M_N_U "u")
+ (VMLAQ_M_N_U "u") (VMINQ_M_S "s") (VMULHQ_M_U "u")
+ (VQADDQ_M_S "s") (VBICQ_M_S "s") (VQSHLQ_M_N_S "s")])
(define_int_attr mode1 [(VCTP8Q "8") (VCTP16Q "16") (VCTP32Q "32")
(VCTP64Q "64") (VCTP8Q_M "8") (VCTP16Q_M "16")
@@ -419,6 +479,47 @@
(define_int_iterator VSRIQ_M_N [VSRIQ_M_N_S VSRIQ_M_N_U])
(define_int_iterator VSUBQ_M [VSUBQ_M_U VSUBQ_M_S])
(define_int_iterator VCVTQ_M_N_TO_F [VCVTQ_M_N_TO_F_U VCVTQ_M_N_TO_F_S])
+(define_int_iterator VHSUBQ_M [VHSUBQ_M_S VHSUBQ_M_U])
+(define_int_iterator VSLIQ_M_N [VSLIQ_M_N_U VSLIQ_M_N_S])
+(define_int_iterator VRSHLQ_M [VRSHLQ_M_S VRSHLQ_M_U])
+(define_int_iterator VMINQ_M [VMINQ_M_S VMINQ_M_U])
+(define_int_iterator VMULLBQ_INT_M [VMULLBQ_INT_M_U VMULLBQ_INT_M_S])
+(define_int_iterator VMULHQ_M [VMULHQ_M_S VMULHQ_M_U])
+(define_int_iterator VMULQ_M [VMULQ_M_S VMULQ_M_U])
+(define_int_iterator VHSUBQ_M_N [VHSUBQ_M_N_S VHSUBQ_M_N_U])
+(define_int_iterator VHADDQ_M_N [VHADDQ_M_N_S VHADDQ_M_N_U])
+(define_int_iterator VORRQ_M [VORRQ_M_S VORRQ_M_U])
+(define_int_iterator VRMULHQ_M [VRMULHQ_M_U VRMULHQ_M_S])
+(define_int_iterator VQADDQ_M [VQADDQ_M_U VQADDQ_M_S])
+(define_int_iterator VRSHRQ_M_N [VRSHRQ_M_N_S VRSHRQ_M_N_U])
+(define_int_iterator VQSUBQ_M_N [VQSUBQ_M_N_U VQSUBQ_M_N_S])
+(define_int_iterator VADDQ_M [VADDQ_M_U VADDQ_M_S])
+(define_int_iterator VORNQ_M [VORNQ_M_U VORNQ_M_S])
+(define_int_iterator VRHADDQ_M [VRHADDQ_M_U VRHADDQ_M_S])
+(define_int_iterator VQSHLQ_M [VQSHLQ_M_U VQSHLQ_M_S])
+(define_int_iterator VANDQ_M [VANDQ_M_U VANDQ_M_S])
+(define_int_iterator VBICQ_M [VBICQ_M_U VBICQ_M_S])
+(define_int_iterator VSHLQ_M_N [VSHLQ_M_N_S VSHLQ_M_N_U])
+(define_int_iterator VCADDQ_ROT270_M [VCADDQ_ROT270_M_U VCADDQ_ROT270_M_S])
+(define_int_iterator VQRSHLQ_M [VQRSHLQ_M_U VQRSHLQ_M_S])
+(define_int_iterator VQADDQ_M_N [VQADDQ_M_N_U VQADDQ_M_N_S])
+(define_int_iterator VADDQ_M_N [VADDQ_M_N_S VADDQ_M_N_U])
+(define_int_iterator VMAXQ_M [VMAXQ_M_S VMAXQ_M_U])
+(define_int_iterator VQSUBQ_M [VQSUBQ_M_U VQSUBQ_M_S])
+(define_int_iterator VMLASQ_M_N [VMLASQ_M_N_U VMLASQ_M_N_S])
+(define_int_iterator VMLADAVAQ_P [VMLADAVAQ_P_U VMLADAVAQ_P_S])
+(define_int_iterator VBRSRQ_M_N [VBRSRQ_M_N_U VBRSRQ_M_N_S])
+(define_int_iterator VMULQ_M_N [VMULQ_M_N_U VMULQ_M_N_S])
+(define_int_iterator VCADDQ_ROT90_M [VCADDQ_ROT90_M_U VCADDQ_ROT90_M_S])
+(define_int_iterator VMULLTQ_INT_M [VMULLTQ_INT_M_S VMULLTQ_INT_M_U])
+(define_int_iterator VEORQ_M [VEORQ_M_S VEORQ_M_U])
+(define_int_iterator VSHRQ_M_N [VSHRQ_M_N_S VSHRQ_M_N_U])
+(define_int_iterator VSUBQ_M_N [VSUBQ_M_N_S VSUBQ_M_N_U])
+(define_int_iterator VHADDQ_M [VHADDQ_M_S VHADDQ_M_U])
+(define_int_iterator VABDQ_M [VABDQ_M_S VABDQ_M_U])
+(define_int_iterator VMLAQ_M_N [VMLAQ_M_N_S VMLAQ_M_N_U])
+(define_int_iterator VQSHLQ_M_N [VQSHLQ_M_N_S VQSHLQ_M_N_U])
+
(define_insn "*mve_mov<mode>"
[(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w,w,r,w,Us")
@@ -5793,3 +5894,1023 @@
"vpst\;vcvtt.f%#<V_sz_elem>.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
+;;
+;; [vabdq_m_s, vabdq_m_u])
+;;
+(define_insn "mve_vabdq_m_<supf><mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:MVE_2 3 "s_register_operand" "w")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VABDQ_M))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vabdt.<supf>%#<V_sz_elem> %q0, %q2, %q3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vaddq_m_n_s, vaddq_m_n_u])
+;;
+(define_insn "mve_vaddq_m_n_<supf><mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:<V_elem> 3 "s_register_operand" "r")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VADDQ_M_N))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vaddt.i%#<V_sz_elem> %q0, %q2, %3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vaddq_m_u, vaddq_m_s])
+;;
+(define_insn "mve_vaddq_m_<supf><mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:MVE_2 3 "s_register_operand" "w")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VADDQ_M))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vaddt.i%#<V_sz_elem> %q0, %q2, %q3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vandq_m_u, vandq_m_s])
+;;
+(define_insn "mve_vandq_m_<supf><mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:MVE_2 3 "s_register_operand" "w")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VANDQ_M))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vandt %q0, %q2, %q3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vbicq_m_u, vbicq_m_s])
+;;
+(define_insn "mve_vbicq_m_<supf><mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:MVE_2 3 "s_register_operand" "w")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VBICQ_M))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vbict %q0, %q2, %q3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vbrsrq_m_n_u, vbrsrq_m_n_s])
+;;
+(define_insn "mve_vbrsrq_m_n_<supf><mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:SI 3 "s_register_operand" "r")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VBRSRQ_M_N))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vbrsrt.%#<V_sz_elem> %q0, %q2, %3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vcaddq_rot270_m_u, vcaddq_rot270_m_s])
+;;
+(define_insn "mve_vcaddq_rot270_m_<supf><mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:MVE_2 3 "s_register_operand" "w")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VCADDQ_ROT270_M))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vcaddt.i%#<V_sz_elem> %q0, %q2, %q3, #270"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vcaddq_rot90_m_u, vcaddq_rot90_m_s])
+;;
+(define_insn "mve_vcaddq_rot90_m_<supf><mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:MVE_2 3 "s_register_operand" "w")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VCADDQ_ROT90_M))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vcaddt.i%#<V_sz_elem> %q0, %q2, %q3, #90"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [veorq_m_s, veorq_m_u])
+;;
+(define_insn "mve_veorq_m_<supf><mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:MVE_2 3 "s_register_operand" "w")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VEORQ_M))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;veort %q0, %q2, %q3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vhaddq_m_n_s, vhaddq_m_n_u])
+;;
+(define_insn "mve_vhaddq_m_n_<supf><mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:<V_elem> 3 "s_register_operand" "r")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VHADDQ_M_N))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vhaddt.<supf>%#<V_sz_elem> %q0, %q2, %3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vhaddq_m_s, vhaddq_m_u])
+;;
+(define_insn "mve_vhaddq_m_<supf><mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:MVE_2 3 "s_register_operand" "w")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VHADDQ_M))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vhaddt.<supf>%#<V_sz_elem> %q0, %q2, %q3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vhsubq_m_n_s, vhsubq_m_n_u])
+;;
+(define_insn "mve_vhsubq_m_n_<supf><mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:<V_elem> 3 "s_register_operand" "r")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VHSUBQ_M_N))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vhsubt.<supf>%#<V_sz_elem> %q0, %q2, %3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vhsubq_m_s, vhsubq_m_u])
+;;
+(define_insn "mve_vhsubq_m_<supf><mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:MVE_2 3 "s_register_operand" "w")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VHSUBQ_M))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vhsubt.<supf>%#<V_sz_elem> %q0, %q2, %q3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vmaxq_m_s, vmaxq_m_u])
+;;
+(define_insn "mve_vmaxq_m_<supf><mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:MVE_2 3 "s_register_operand" "w")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VMAXQ_M))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vmaxt.<supf>%#<V_sz_elem> %q0, %q2, %q3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vminq_m_s, vminq_m_u])
+;;
+(define_insn "mve_vminq_m_<supf><mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:MVE_2 3 "s_register_operand" "w")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VMINQ_M))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vmint.<supf>%#<V_sz_elem> %q0, %q2, %q3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vmladavaq_p_u, vmladavaq_p_s])
+;;
+(define_insn "mve_vmladavaq_p_<supf><mode>"
+ [
+ (set (match_operand:SI 0 "s_register_operand" "=e")
+ (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:MVE_2 3 "s_register_operand" "w")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VMLADAVAQ_P))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vmladavat.<supf>%#<V_sz_elem> %0, %q2, %q3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vmlaq_m_n_s, vmlaq_m_n_u])
+;;
+(define_insn "mve_vmlaq_m_n_<supf><mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:<V_elem> 3 "s_register_operand" "r")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VMLAQ_M_N))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vmlat.<supf>%#<V_sz_elem> %q0, %q2, %3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vmlasq_m_n_u, vmlasq_m_n_s])
+;;
+(define_insn "mve_vmlasq_m_n_<supf><mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:<V_elem> 3 "s_register_operand" "r")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VMLASQ_M_N))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vmlast.<supf>%#<V_sz_elem> %q0, %q2, %3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vmulhq_m_s, vmulhq_m_u])
+;;
+(define_insn "mve_vmulhq_m_<supf><mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:MVE_2 3 "s_register_operand" "w")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VMULHQ_M))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vmulht.<supf>%#<V_sz_elem> %q0, %q2, %q3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vmullbq_int_m_u, vmullbq_int_m_s])
+;;
+(define_insn "mve_vmullbq_int_m_<supf><mode>"
+ [
+ (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
+ (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:MVE_2 3 "s_register_operand" "w")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VMULLBQ_INT_M))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vmullbt.<supf>%#<V_sz_elem> %q0, %q2, %q3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vmulltq_int_m_s, vmulltq_int_m_u])
+;;
+(define_insn "mve_vmulltq_int_m_<supf><mode>"
+ [
+ (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
+ (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:MVE_2 3 "s_register_operand" "w")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VMULLTQ_INT_M))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vmulltt.<supf>%#<V_sz_elem> %q0, %q2, %q3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vmulq_m_n_u, vmulq_m_n_s])
+;;
+(define_insn "mve_vmulq_m_n_<supf><mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:<V_elem> 3 "s_register_operand" "r")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VMULQ_M_N))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vmult.i%#<V_sz_elem> %q0, %q2, %3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vmulq_m_s, vmulq_m_u])
+;;
+(define_insn "mve_vmulq_m_<supf><mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:MVE_2 3 "s_register_operand" "w")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VMULQ_M))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vmult.i%#<V_sz_elem> %q0, %q2, %q3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vornq_m_u, vornq_m_s])
+;;
+(define_insn "mve_vornq_m_<supf><mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:MVE_2 3 "s_register_operand" "w")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VORNQ_M))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vornt %q0, %q2, %q3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vorrq_m_s, vorrq_m_u])
+;;
+(define_insn "mve_vorrq_m_<supf><mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:MVE_2 3 "s_register_operand" "w")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VORRQ_M))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vorrt %q0, %q2, %q3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vqaddq_m_n_u, vqaddq_m_n_s])
+;;
+(define_insn "mve_vqaddq_m_n_<supf><mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:<V_elem> 3 "s_register_operand" "r")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VQADDQ_M_N))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vqaddt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vqaddq_m_u, vqaddq_m_s])
+;;
+(define_insn "mve_vqaddq_m_<supf><mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:MVE_2 3 "s_register_operand" "w")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VQADDQ_M))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vqaddt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vqdmlahq_m_n_s])
+;;
+(define_insn "mve_vqdmlahq_m_n_s<mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:<V_elem> 3 "s_register_operand" "r")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VQDMLAHQ_M_N_S))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vqdmlaht.s%#<V_sz_elem>\t%q0, %q2, %3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vqrdmlahq_m_n_s])
+;;
+(define_insn "mve_vqrdmlahq_m_n_s<mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:<V_elem> 3 "s_register_operand" "r")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VQRDMLAHQ_M_N_S))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vqrdmlaht.s%#<V_sz_elem>\t%q0, %q2, %3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vqrdmlashq_m_n_s])
+;;
+(define_insn "mve_vqrdmlashq_m_n_s<mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:<V_elem> 3 "s_register_operand" "r")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VQRDMLASHQ_M_N_S))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vqrdmlasht.s%#<V_sz_elem>\t%q0, %q2, %3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vqrshlq_m_u, vqrshlq_m_s])
+;;
+(define_insn "mve_vqrshlq_m_<supf><mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:MVE_2 3 "s_register_operand" "w")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VQRSHLQ_M))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vqrshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vqshlq_m_n_s, vqshlq_m_n_u])
+;;
+(define_insn "mve_vqshlq_m_n_<supf><mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:SI 3 "immediate_operand" "i")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VQSHLQ_M_N))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vqshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vqshlq_m_u, vqshlq_m_s])
+;;
+(define_insn "mve_vqshlq_m_<supf><mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:MVE_2 3 "s_register_operand" "w")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VQSHLQ_M))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vqshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vqsubq_m_n_u, vqsubq_m_n_s])
+;;
+(define_insn "mve_vqsubq_m_n_<supf><mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:<V_elem> 3 "s_register_operand" "r")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VQSUBQ_M_N))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vqsubt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vqsubq_m_u, vqsubq_m_s])
+;;
+(define_insn "mve_vqsubq_m_<supf><mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:MVE_2 3 "s_register_operand" "w")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VQSUBQ_M))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vqsubt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vrhaddq_m_u, vrhaddq_m_s])
+;;
+(define_insn "mve_vrhaddq_m_<supf><mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:MVE_2 3 "s_register_operand" "w")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VRHADDQ_M))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vrhaddt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vrmulhq_m_u, vrmulhq_m_s])
+;;
+(define_insn "mve_vrmulhq_m_<supf><mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:MVE_2 3 "s_register_operand" "w")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VRMULHQ_M))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vrmulht.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vrshlq_m_s, vrshlq_m_u])
+;;
+(define_insn "mve_vrshlq_m_<supf><mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:MVE_2 3 "s_register_operand" "w")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VRSHLQ_M))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vrshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vrshrq_m_n_s, vrshrq_m_n_u])
+;;
+(define_insn "mve_vrshrq_m_n_<supf><mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:SI 3 "<MVE_pred2>" "<MVE_constraint2>")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VRSHRQ_M_N))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vrshrt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vshlq_m_n_s, vshlq_m_n_u])
+;;
+(define_insn "mve_vshlq_m_n_<supf><mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:SI 3 "immediate_operand" "i")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VSHLQ_M_N))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vshrq_m_n_s, vshrq_m_n_u])
+;;
+(define_insn "mve_vshrq_m_n_<supf><mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:SI 3 "<MVE_pred2>" "<MVE_constraint2>")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VSHRQ_M_N))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vshrt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vsliq_m_n_u, vsliq_m_n_s])
+;;
+(define_insn "mve_vsliq_m_n_<supf><mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:SI 3 "<MVE_pred>" "<MVE_constraint>")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VSLIQ_M_N))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vslit.%#<V_sz_elem>\t%q0, %q2, %3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vsubq_m_n_s, vsubq_m_n_u])
+;;
+(define_insn "mve_vsubq_m_n_<supf><mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:<V_elem> 3 "s_register_operand" "r")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VSUBQ_M_N))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vsubt.i%#<V_sz_elem>\t%q0, %q2, %3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vhcaddq_rot270_m_s])
+;;
+(define_insn "mve_vhcaddq_rot270_m_s<mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:MVE_2 3 "s_register_operand" "w")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VHCADDQ_ROT270_M_S))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vhcaddt.s%#<V_sz_elem>\t%q0, %q2, %q3, #270"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vhcaddq_rot90_m_s])
+;;
+(define_insn "mve_vhcaddq_rot90_m_s<mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:MVE_2 3 "s_register_operand" "w")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VHCADDQ_ROT90_M_S))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vhcaddt.s%#<V_sz_elem>\t%q0, %q2, %q3, #90"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vmladavaxq_p_s])
+;;
+(define_insn "mve_vmladavaxq_p_s<mode>"
+ [
+ (set (match_operand:SI 0 "s_register_operand" "=e")
+ (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:MVE_2 3 "s_register_operand" "w")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VMLADAVAXQ_P_S))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vmladavaxt.s%#<V_sz_elem>\t%0, %q2, %q3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vmlsdavaq_p_s])
+;;
+(define_insn "mve_vmlsdavaq_p_s<mode>"
+ [
+ (set (match_operand:SI 0 "s_register_operand" "=e")
+ (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:MVE_2 3 "s_register_operand" "w")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VMLSDAVAQ_P_S))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vmlsdavat.s%#<V_sz_elem>\t%0, %q2, %q3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vmlsdavaxq_p_s])
+;;
+(define_insn "mve_vmlsdavaxq_p_s<mode>"
+ [
+ (set (match_operand:SI 0 "s_register_operand" "=e")
+ (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:MVE_2 3 "s_register_operand" "w")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VMLSDAVAXQ_P_S))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vmlsdavaxt.s%#<V_sz_elem>\t%0, %q2, %q3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vqdmladhq_m_s])
+;;
+(define_insn "mve_vqdmladhq_m_s<mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:MVE_2 3 "s_register_operand" "w")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VQDMLADHQ_M_S))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vqdmladht.s%#<V_sz_elem>\t%q0, %q2, %q3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vqdmladhxq_m_s])
+;;
+(define_insn "mve_vqdmladhxq_m_s<mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:MVE_2 3 "s_register_operand" "w")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VQDMLADHXQ_M_S))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vqdmladhxt.s%#<V_sz_elem>\t%q0, %q2, %q3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vqdmlsdhq_m_s])
+;;
+(define_insn "mve_vqdmlsdhq_m_s<mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:MVE_2 3 "s_register_operand" "w")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VQDMLSDHQ_M_S))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vqdmlsdht.s%#<V_sz_elem>\t%q0, %q2, %q3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vqdmlsdhxq_m_s])
+;;
+(define_insn "mve_vqdmlsdhxq_m_s<mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:MVE_2 3 "s_register_operand" "w")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VQDMLSDHXQ_M_S))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vqdmlsdhxt.s%#<V_sz_elem>\t%q0, %q2, %q3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vqdmulhq_m_n_s])
+;;
+(define_insn "mve_vqdmulhq_m_n_s<mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:<V_elem> 3 "s_register_operand" "r")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VQDMULHQ_M_N_S))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vqdmulht.s%#<V_sz_elem>\t%q0, %q2, %3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vqdmulhq_m_s])
+;;
+(define_insn "mve_vqdmulhq_m_s<mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:MVE_2 3 "s_register_operand" "w")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VQDMULHQ_M_S))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vqdmulht.s%#<V_sz_elem>\t%q0, %q2, %q3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vqrdmladhq_m_s])
+;;
+(define_insn "mve_vqrdmladhq_m_s<mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:MVE_2 3 "s_register_operand" "w")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VQRDMLADHQ_M_S))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vqrdmladht.s%#<V_sz_elem>\t%q0, %q2, %q3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vqrdmladhxq_m_s])
+;;
+(define_insn "mve_vqrdmladhxq_m_s<mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:MVE_2 3 "s_register_operand" "w")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VQRDMLADHXQ_M_S))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vqrdmladhxt.s%#<V_sz_elem>\t%q0, %q2, %q3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vqrdmlsdhq_m_s])
+;;
+(define_insn "mve_vqrdmlsdhq_m_s<mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:MVE_2 3 "s_register_operand" "w")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VQRDMLSDHQ_M_S))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vqrdmlsdht.s%#<V_sz_elem>\t%q0, %q2, %q3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vqrdmlsdhxq_m_s])
+;;
+(define_insn "mve_vqrdmlsdhxq_m_s<mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:MVE_2 3 "s_register_operand" "w")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VQRDMLSDHXQ_M_S))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vqrdmlsdhxt.s%#<V_sz_elem>\t%q0, %q2, %q3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vqrdmulhq_m_n_s])
+;;
+(define_insn "mve_vqrdmulhq_m_n_s<mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:<V_elem> 3 "s_register_operand" "r")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VQRDMULHQ_M_N_S))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vqrdmulht.s%#<V_sz_elem>\t%q0, %q2, %3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
+;;
+;; [vqrdmulhq_m_s])
+;;
+(define_insn "mve_vqrdmulhq_m_s<mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:MVE_2 3 "s_register_operand" "w")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VQRDMULHQ_M_S))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vqrdmulht.s%#<V_sz_elem>\t%q0, %q2, %q3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index f4e117c5117..276c55f8822 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,317 @@
+2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
+ Mihail Ionescu <mihail.ionescu@arm.com>
+ Srinath Parvathaneni <srinath.parvathaneni@arm.com>
+
+ * gcc.target/arm/mve/intrinsics/vabdq_m_s16.c: New test.
+ * gcc.target/arm/mve/intrinsics/vabdq_m_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vabdq_m_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vabdq_m_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vabdq_m_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vabdq_m_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vaddq_m_n_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vaddq_m_n_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vaddq_m_n_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vaddq_m_n_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vaddq_m_n_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vaddq_m_n_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vaddq_m_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vaddq_m_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vaddq_m_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vaddq_m_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vaddq_m_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vaddq_m_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vandq_m_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vandq_m_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vandq_m_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vandq_m_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vandq_m_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vandq_m_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vbicq_m_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vbicq_m_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vbicq_m_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vbicq_m_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vbicq_m_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vbicq_m_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/veorq_m_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/veorq_m_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/veorq_m_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/veorq_m_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/veorq_m_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/veorq_m_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhaddq_m_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhaddq_m_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhaddq_m_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhaddq_m_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhaddq_m_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhaddq_m_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhsubq_m_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhsubq_m_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhsubq_m_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhsubq_m_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhsubq_m_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhsubq_m_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vminq_m_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vminq_m_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vminq_m_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vminq_m_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vminq_m_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vminq_m_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmladavaq_p_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmladavaq_p_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmladavaq_p_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmladavaq_p_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmladavaq_p_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmladavaxq_p_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmladavaxq_p_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmladavaxq_p_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmlasq_m_n_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmulhq_m_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmulhq_m_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmulhq_m_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmulhq_m_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmulhq_m_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmulhq_m_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmullbq_int_m_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmullbq_int_m_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmullbq_int_m_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmullbq_int_m_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmullbq_int_m_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmullbq_int_m_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmulltq_int_m_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmulltq_int_m_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmulltq_int_m_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmulltq_int_m_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmulltq_int_m_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmulltq_int_m_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmulq_m_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmulq_m_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmulq_m_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmulq_m_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmulq_m_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmulq_m_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vornq_m_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vornq_m_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vornq_m_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vornq_m_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vornq_m_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vornq_m_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vorrq_m_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vorrq_m_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vorrq_m_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vorrq_m_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vorrq_m_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vorrq_m_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqdmladhq_m_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqdmladhq_m_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqdmladhq_m_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqdmulhq_m_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqdmulhq_m_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqdmulhq_m_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqrshlq_m_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqrshlq_m_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqrshlq_m_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqrshlq_m_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqrshlq_m_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqrshlq_m_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqshlq_m_n_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqshlq_m_n_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqshlq_m_n_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqshlq_m_n_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqshlq_m_n_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqshlq_m_n_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqshlq_m_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqshlq_m_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqshlq_m_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqshlq_m_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqshlq_m_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqshlq_m_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrhaddq_m_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrhaddq_m_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrhaddq_m_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrhaddq_m_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrhaddq_m_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrhaddq_m_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrmulhq_m_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrmulhq_m_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrmulhq_m_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrmulhq_m_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrmulhq_m_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrmulhq_m_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrshlq_m_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrshlq_m_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrshlq_m_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrshrq_m_n_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vshrq_m_n_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vshrq_m_n_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vshrq_m_n_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vshrq_m_n_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vshrq_m_n_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vshrq_m_n_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vsliq_m_n_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vsliq_m_n_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vsliq_m_n_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vsliq_m_n_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vsliq_m_n_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vsliq_m_n_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c: Likewise.
+
2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
Mihail Ionescu <mihail.ionescu@arm.com>
Srinath Parvathaneni <srinath.parvathaneni@arm.com>
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s16.c
new file mode 100644
index 00000000000..a51b4cce6c1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vabdq_m_s16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vabdt.s16" } } */
+
+int16x8_t
+foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vabdq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vabdt.s16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s32.c
new file mode 100644
index 00000000000..cddc068884f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vabdq_m_s32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vabdt.s32" } } */
+
+int32x4_t
+foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vabdq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vabdt.s32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s8.c
new file mode 100644
index 00000000000..d6cbba93ce9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vabdq_m_s8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vabdt.s8" } } */
+
+int8x16_t
+foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vabdq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vabdt.s8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u16.c
new file mode 100644
index 00000000000..b35d8d66ae8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+ return vabdq_m_u16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vabdt.u16" } } */
+
+uint16x8_t
+foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+ return vabdq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vabdt.u16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u32.c
new file mode 100644
index 00000000000..3055fc296ba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+{
+ return vabdq_m_u32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vabdt.u32" } } */
+
+uint32x4_t
+foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+{
+ return vabdq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vabdt.u32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u8.c
new file mode 100644
index 00000000000..03be33ffbdd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint8x16_t
+foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+{
+ return vabdq_m_u8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vabdt.u8" } } */
+
+uint8x16_t
+foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+{
+ return vabdq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vabdt.u8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s16.c
new file mode 100644
index 00000000000..c18e1d0301d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
+{
+ return vaddq_m_n_s16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.i16" } } */
+
+int16x8_t
+foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
+{
+ return vaddq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.i16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s32.c
new file mode 100644
index 00000000000..37b4443980c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
+{
+ return vaddq_m_n_s32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.i32" } } */
+
+int32x4_t
+foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
+{
+ return vaddq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.i32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s8.c
new file mode 100644
index 00000000000..89cacc2010d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
+{
+ return vaddq_m_n_s8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.i8" } } */
+
+int8x16_t
+foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
+{
+ return vaddq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.i8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u16.c
new file mode 100644
index 00000000000..9039f51ecaa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p)
+{
+ return vaddq_m_n_u16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.i16" } } */
+
+uint16x8_t
+foo1 (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p)
+{
+ return vaddq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.i16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u32.c
new file mode 100644
index 00000000000..fdf11aa4a36
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p)
+{
+ return vaddq_m_n_u32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.i32" } } */
+
+uint32x4_t
+foo1 (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p)
+{
+ return vaddq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.i32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u8.c
new file mode 100644
index 00000000000..35b71db32d2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint8x16_t
+foo (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p)
+{
+ return vaddq_m_n_u8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.i8" } } */
+
+uint8x16_t
+foo1 (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p)
+{
+ return vaddq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.i8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s16.c
new file mode 100644
index 00000000000..337b7664873
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vaddq_m_s16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.i16" } } */
+
+int16x8_t
+foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vaddq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.i16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s32.c
new file mode 100644
index 00000000000..5832354caa3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vaddq_m_s32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.i32" } } */
+
+int32x4_t
+foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vaddq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.i32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s8.c
new file mode 100644
index 00000000000..9c40875400f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vaddq_m_s8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.i8" } } */
+
+int8x16_t
+foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vaddq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.i8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u16.c
new file mode 100644
index 00000000000..9bab84ec5e3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+ return vaddq_m_u16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.i16" } } */
+
+uint16x8_t
+foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+ return vaddq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.i16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u32.c
new file mode 100644
index 00000000000..b758ca6ee11
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+{
+ return vaddq_m_u32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.i32" } } */
+
+uint32x4_t
+foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+{
+ return vaddq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.i32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u8.c
new file mode 100644
index 00000000000..f5918d6b2dc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint8x16_t
+foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+{
+ return vaddq_m_u8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.i8" } } */
+
+uint8x16_t
+foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+{
+ return vaddq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.i8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s16.c
new file mode 100644
index 00000000000..aa96d4df216
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vandq_m_s16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vandt" } } */
+
+int16x8_t
+foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vandq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vandt" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s32.c
new file mode 100644
index 00000000000..e266b748058
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vandq_m_s32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vandt" } } */
+
+int32x4_t
+foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vandq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vandt" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s8.c
new file mode 100644
index 00000000000..680d98cf4d2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vandq_m_s8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vandt" } } */
+
+int8x16_t
+foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vandq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vandt" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u16.c
new file mode 100644
index 00000000000..ab5bb9462f8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+ return vandq_m_u16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vandt" } } */
+
+uint16x8_t
+foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+ return vandq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vandt" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u32.c
new file mode 100644
index 00000000000..408a309c16d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+{
+ return vandq_m_u32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vandt" } } */
+
+uint32x4_t
+foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+{
+ return vandq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vandt" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u8.c
new file mode 100644
index 00000000000..0b6338161c1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint8x16_t
+foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+{
+ return vandq_m_u8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vandt" } } */
+
+uint8x16_t
+foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+{
+ return vandq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vandt" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s16.c
new file mode 100644
index 00000000000..3e1e8a20e56
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vbicq_m_s16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbict" } } */
+
+int16x8_t
+foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vbicq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbict" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s32.c
new file mode 100644
index 00000000000..20b2366d44b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vbicq_m_s32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbict" } } */
+
+int32x4_t
+foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vbicq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbict" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s8.c
new file mode 100644
index 00000000000..a54609daca6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vbicq_m_s8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbict" } } */
+
+int8x16_t
+foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vbicq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbict" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u16.c
new file mode 100644
index 00000000000..18f29b0043e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+ return vbicq_m_u16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbict" } } */
+
+uint16x8_t
+foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+ return vbicq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbict" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u32.c
new file mode 100644
index 00000000000..840f613bd21
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+{
+ return vbicq_m_u32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbict" } } */
+
+uint32x4_t
+foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+{
+ return vbicq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbict" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u8.c
new file mode 100644
index 00000000000..7ee61037426
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint8x16_t
+foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+{
+ return vbicq_m_u8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbict" } } */
+
+uint8x16_t
+foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+{
+ return vbicq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbict" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c
new file mode 100644
index 00000000000..fe011ec0ede
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t inactive, int16x8_t a, int32_t b, mve_pred16_t p)
+{
+ return vbrsrq_m_n_s16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbrsrt.16" } } */
+
+int16x8_t
+foo1 (int16x8_t inactive, int16x8_t a, int32_t b, mve_pred16_t p)
+{
+ return vbrsrq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbrsrt.16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c
new file mode 100644
index 00000000000..22b2673889f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
+{
+ return vbrsrq_m_n_s32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbrsrt.32" } } */
+
+int32x4_t
+foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
+{
+ return vbrsrq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbrsrt.32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c
new file mode 100644
index 00000000000..fab7ec0acdb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t inactive, int8x16_t a, int32_t b, mve_pred16_t p)
+{
+ return vbrsrq_m_n_s8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbrsrt.8" } } */
+
+int8x16_t
+foo1 (int8x16_t inactive, int8x16_t a, int32_t b, mve_pred16_t p)
+{
+ return vbrsrq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbrsrt.8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c
new file mode 100644
index 00000000000..6b0a5c3b28f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t inactive, uint16x8_t a, int32_t b, mve_pred16_t p)
+{
+ return vbrsrq_m_n_u16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbrsrt.16" } } */
+
+uint16x8_t
+foo1 (uint16x8_t inactive, uint16x8_t a, int32_t b, mve_pred16_t p)
+{
+ return vbrsrq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbrsrt.16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c
new file mode 100644
index 00000000000..68e40150b59
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint32x4_t inactive, uint32x4_t a, int32_t b, mve_pred16_t p)
+{
+ return vbrsrq_m_n_u32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbrsrt.32" } } */
+
+uint32x4_t
+foo1 (uint32x4_t inactive, uint32x4_t a, int32_t b, mve_pred16_t p)
+{
+ return vbrsrq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbrsrt.32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c
new file mode 100644
index 00000000000..d9956dcb1f1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint8x16_t
+foo (uint8x16_t inactive, uint8x16_t a, int32_t b, mve_pred16_t p)
+{
+ return vbrsrq_m_n_u8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbrsrt.8" } } */
+
+uint8x16_t
+foo1 (uint8x16_t inactive, uint8x16_t a, int32_t b, mve_pred16_t p)
+{
+ return vbrsrq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbrsrt.8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s16.c
new file mode 100644
index 00000000000..f9068581ad2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vcaddq_rot270_m_s16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcaddt.i16" } } */
+
+int16x8_t
+foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vcaddq_rot270_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcaddt.i16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s32.c
new file mode 100644
index 00000000000..87d347c4ae9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vcaddq_rot270_m_s32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcaddt.i32" } } */
+
+int32x4_t
+foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vcaddq_rot270_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcaddt.i32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s8.c
new file mode 100644
index 00000000000..708d174d774
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vcaddq_rot270_m_s8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcaddt.i8" } } */
+
+int8x16_t
+foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vcaddq_rot270_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcaddt.i8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u16.c
new file mode 100644
index 00000000000..070a4fcc66d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+ return vcaddq_rot270_m_u16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcaddt.i16" } } */
+
+uint16x8_t
+foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+ return vcaddq_rot270_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcaddt.i16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u32.c
new file mode 100644
index 00000000000..9f75313eefc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+{
+ return vcaddq_rot270_m_u32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcaddt.i32" } } */
+
+uint32x4_t
+foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+{
+ return vcaddq_rot270_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcaddt.i32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u8.c
new file mode 100644
index 00000000000..4cb5a30c719
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint8x16_t
+foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+{
+ return vcaddq_rot270_m_u8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcaddt.i8" } } */
+
+uint8x16_t
+foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+{
+ return vcaddq_rot270_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcaddt.i8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s16.c
new file mode 100644
index 00000000000..30da2de5b9c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vcaddq_rot90_m_s16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcaddt.i16" } } */
+
+int16x8_t
+foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vcaddq_rot90_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcaddt.i16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s32.c
new file mode 100644
index 00000000000..4ee23c284fc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vcaddq_rot90_m_s32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcaddt.i32" } } */
+
+int32x4_t
+foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vcaddq_rot90_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcaddt.i32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s8.c
new file mode 100644
index 00000000000..42f83a62bbf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vcaddq_rot90_m_s8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcaddt.i8" } } */
+
+int8x16_t
+foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vcaddq_rot90_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcaddt.i8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u16.c
new file mode 100644
index 00000000000..1bbaaf5df1f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+ return vcaddq_rot90_m_u16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcaddt.i16" } } */
+
+uint16x8_t
+foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+ return vcaddq_rot90_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcaddt.i16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u32.c
new file mode 100644
index 00000000000..16ac73d96c2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+{
+ return vcaddq_rot90_m_u32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcaddt.i32" } } */
+
+uint32x4_t
+foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+{
+ return vcaddq_rot90_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcaddt.i32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u8.c
new file mode 100644
index 00000000000..bd4fdba125f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint8x16_t
+foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+{
+ return vcaddq_rot90_m_u8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcaddt.i8" } } */
+
+uint8x16_t
+foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+{
+ return vcaddq_rot90_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcaddt.i8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s16.c
new file mode 100644
index 00000000000..7c3ff0d501e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return veorq_m_s16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "veort" } } */
+
+int16x8_t
+foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return veorq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "veort" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s32.c
new file mode 100644
index 00000000000..a4e62e05ef9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return veorq_m_s32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "veort" } } */
+
+int32x4_t
+foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return veorq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "veort" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s8.c
new file mode 100644
index 00000000000..e7c91aafa7f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return veorq_m_s8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "veort" } } */
+
+int8x16_t
+foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return veorq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "veort" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u16.c
new file mode 100644
index 00000000000..9b2a380926d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+ return veorq_m_u16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "veort" } } */
+
+uint16x8_t
+foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+ return veorq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "veort" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u32.c
new file mode 100644
index 00000000000..fdfc5de15c1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+{
+ return veorq_m_u32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "veort" } } */
+
+uint32x4_t
+foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+{
+ return veorq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "veort" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u8.c
new file mode 100644
index 00000000000..741e1860b08
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint8x16_t
+foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+{
+ return veorq_m_u8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "veort" } } */
+
+uint8x16_t
+foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+{
+ return veorq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "veort" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c
new file mode 100644
index 00000000000..72cc006e56d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
+{
+ return vhaddq_m_n_s16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhaddt.s16" } } */
+
+int16x8_t
+foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
+{
+ return vhaddq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhaddt.s16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c
new file mode 100644
index 00000000000..84c5f5a0c4f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
+{
+ return vhaddq_m_n_s32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhaddt.s32" } } */
+
+int32x4_t
+foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
+{
+ return vhaddq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhaddt.s32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c
new file mode 100644
index 00000000000..2a391cb1dd4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
+{
+ return vhaddq_m_n_s8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhaddt.s8" } } */
+
+int8x16_t
+foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
+{
+ return vhaddq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhaddt.s8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c
new file mode 100644
index 00000000000..3d6ce0e41b1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p)
+{
+ return vhaddq_m_n_u16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhaddt.u16" } } */
+
+uint16x8_t
+foo1 (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p)
+{
+ return vhaddq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhaddt.u16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c
new file mode 100644
index 00000000000..6acad1b931a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p)
+{
+ return vhaddq_m_n_u32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhaddt.u32" } } */
+
+uint32x4_t
+foo1 (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p)
+{
+ return vhaddq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhaddt.u32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c
new file mode 100644
index 00000000000..709c8d0a582
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint8x16_t
+foo (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p)
+{
+ return vhaddq_m_n_u8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhaddt.u8" } } */
+
+uint8x16_t
+foo1 (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p)
+{
+ return vhaddq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhaddt.u8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s16.c
new file mode 100644
index 00000000000..421116a18bd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vhaddq_m_s16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhaddt.s16" } } */
+
+int16x8_t
+foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vhaddq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhaddt.s16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s32.c
new file mode 100644
index 00000000000..2f9b1bbcb36
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vhaddq_m_s32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhaddt.s32" } } */
+
+int32x4_t
+foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vhaddq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhaddt.s32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s8.c
new file mode 100644
index 00000000000..b9cec7db674
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vhaddq_m_s8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhaddt.s8" } } */
+
+int8x16_t
+foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vhaddq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhaddt.s8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u16.c
new file mode 100644
index 00000000000..8045faf680f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+ return vhaddq_m_u16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhaddt.u16" } } */
+
+uint16x8_t
+foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+ return vhaddq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhaddt.u16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u32.c
new file mode 100644
index 00000000000..c65a2e04e0e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+{
+ return vhaddq_m_u32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhaddt.u32" } } */
+
+uint32x4_t
+foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+{
+ return vhaddq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhaddt.u32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u8.c
new file mode 100644
index 00000000000..164098a45f8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint8x16_t
+foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+{
+ return vhaddq_m_u8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhaddt.u8" } } */
+
+uint8x16_t
+foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+{
+ return vhaddq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhaddt.u8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s16.c
new file mode 100644
index 00000000000..bb9aa150eaa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vhcaddq_rot270_m_s16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhcaddt.s16" } } */
+
+int16x8_t
+foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vhcaddq_rot270_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhcaddt.s16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s32.c
new file mode 100644
index 00000000000..d1a0f3624dd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vhcaddq_rot270_m_s32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhcaddt.s32" } } */
+
+int32x4_t
+foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vhcaddq_rot270_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhcaddt.s32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s8.c
new file mode 100644
index 00000000000..65ba17485ed
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vhcaddq_rot270_m_s8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhcaddt.s8" } } */
+
+int8x16_t
+foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vhcaddq_rot270_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhcaddt.s8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s16.c
new file mode 100644
index 00000000000..3289c1931d4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vhcaddq_rot90_m_s16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhcaddt.s16" } } */
+
+int16x8_t
+foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vhcaddq_rot90_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhcaddt.s16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s32.c
new file mode 100644
index 00000000000..266c8219ac5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vhcaddq_rot90_m_s32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhcaddt.s32" } } */
+
+int32x4_t
+foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vhcaddq_rot90_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhcaddt.s32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s8.c
new file mode 100644
index 00000000000..b42af7462b6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vhcaddq_rot90_m_s8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhcaddt.s8" } } */
+
+int8x16_t
+foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vhcaddq_rot90_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhcaddt.s8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c
new file mode 100644
index 00000000000..5e283a52a06
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
+{
+ return vhsubq_m_n_s16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhsubt.s16" } } */
+
+int16x8_t
+foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
+{
+ return vhsubq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhsubt.s16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c
new file mode 100644
index 00000000000..ceefcd4468a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
+{
+ return vhsubq_m_n_s32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhsubt.s32" } } */
+
+int32x4_t
+foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
+{
+ return vhsubq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhsubt.s32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c
new file mode 100644
index 00000000000..85dde181c14
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
+{
+ return vhsubq_m_n_s8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhsubt.s8" } } */
+
+int8x16_t
+foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
+{
+ return vhsubq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhsubt.s8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c
new file mode 100644
index 00000000000..ceeb5d432f1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p)
+{
+ return vhsubq_m_n_u16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhsubt.u16" } } */
+
+uint16x8_t
+foo1 (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p)
+{
+ return vhsubq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhsubt.u16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c
new file mode 100644
index 00000000000..b0656bcb5db
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p)
+{
+ return vhsubq_m_n_u32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhsubt.u32" } } */
+
+uint32x4_t
+foo1 (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p)
+{
+ return vhsubq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhsubt.u32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c
new file mode 100644
index 00000000000..a1b9e29c2d5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint8x16_t
+foo (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p)
+{
+ return vhsubq_m_n_u8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhsubt.u8" } } */
+
+uint8x16_t
+foo1 (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p)
+{
+ return vhsubq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhsubt.u8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s16.c
new file mode 100644
index 00000000000..a5cc707b0d1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vhsubq_m_s16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhsubt.s16" } } */
+
+int16x8_t
+foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vhsubq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhsubt.s16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s32.c
new file mode 100644
index 00000000000..7a0322fb8c1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vhsubq_m_s32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhsubt.s32" } } */
+
+int32x4_t
+foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vhsubq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhsubt.s32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s8.c
new file mode 100644
index 00000000000..c9f84d10b8b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vhsubq_m_s8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhsubt.s8" } } */
+
+int8x16_t
+foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vhsubq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhsubt.s8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u16.c
new file mode 100644
index 00000000000..0ea33ae3ba6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+ return vhsubq_m_u16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhsubt.u16" } } */
+
+uint16x8_t
+foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+ return vhsubq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhsubt.u16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u32.c
new file mode 100644
index 00000000000..5ee5da89e66
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+{
+ return vhsubq_m_u32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhsubt.u32" } } */
+
+uint32x4_t
+foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+{
+ return vhsubq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhsubt.u32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u8.c
new file mode 100644
index 00000000000..c5e2130bf8a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint8x16_t
+foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+{
+ return vhsubq_m_u8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhsubt.u8" } } */
+
+uint8x16_t
+foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+{
+ return vhsubq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vhsubt.u8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c
new file mode 100644
index 00000000000..d1ae619e7cd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vmaxq_m_s16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmaxt.s16" } } */
+
+int16x8_t
+foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vmaxq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmaxt.s16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c
new file mode 100644
index 00000000000..7d23817ceab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vmaxq_m_s32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmaxt.s32" } } */
+
+int32x4_t
+foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vmaxq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmaxt.s32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c
new file mode 100644
index 00000000000..3f4f8d0b11f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vmaxq_m_s8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmaxt.s8" } } */
+
+int8x16_t
+foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vmaxq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmaxt.s8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c
new file mode 100644
index 00000000000..6d56612ac9d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+ return vmaxq_m_u16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmaxt.u16" } } */
+
+uint16x8_t
+foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+ return vmaxq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmaxt.u16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c
new file mode 100644
index 00000000000..fd7a4b236ee
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+{
+ return vmaxq_m_u32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmaxt.u32" } } */
+
+uint32x4_t
+foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+{
+ return vmaxq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmaxt.u32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c
new file mode 100644
index 00000000000..885d9ca5b92
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint8x16_t
+foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+{
+ return vmaxq_m_u8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmaxt.u8" } } */
+
+uint8x16_t
+foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+{
+ return vmaxq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmaxt.u8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s16.c
new file mode 100644
index 00000000000..84b8960eb49
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vminq_m_s16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmint.s16" } } */
+
+int16x8_t
+foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vminq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmint.s16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s32.c
new file mode 100644
index 00000000000..6181b85f398
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vminq_m_s32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmint.s32" } } */
+
+int32x4_t
+foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vminq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmint.s32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s8.c
new file mode 100644
index 00000000000..99fe68eea82
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vminq_m_s8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmint.s8" } } */
+
+int8x16_t
+foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vminq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmint.s8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u16.c
new file mode 100644
index 00000000000..a3f307defd1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+ return vminq_m_u16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmint.u16" } } */
+
+uint16x8_t
+foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+ return vminq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmint.u16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u32.c
new file mode 100644
index 00000000000..10b17c6fa3c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+{
+ return vminq_m_u32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmint.u32" } } */
+
+uint32x4_t
+foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+{
+ return vminq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmint.u32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u8.c
new file mode 100644
index 00000000000..54898e02faa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint8x16_t
+foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+{
+ return vminq_m_u8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmint.u8" } } */
+
+uint8x16_t
+foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+{
+ return vminq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmint.u8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s16.c
new file mode 100644
index 00000000000..3ec6294e72c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s16.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32_t
+foo (int32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
+{
+ return vmladavaq_p_s16 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vmladavat.s16" } } */
+
+int32_t
+foo1 (int32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
+{
+ return vmladavaq_p (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vmladavat.s16" } } */
+/* { dg-final { scan-assembler "vmladavat.s16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s32.c
new file mode 100644
index 00000000000..5af847df6cb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s32.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32_t
+foo (int32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
+{
+ return vmladavaq_p_s32 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vmladavat.s32" } } */
+
+int32_t
+foo1 (int32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
+{
+ return vmladavaq_p (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vmladavat.s32" } } */
+/* { dg-final { scan-assembler "vmladavat.s32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c
new file mode 100644
index 00000000000..dc3d2303f01
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32_t
+foo (int32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p)
+{
+ return vmladavaq_p_s8 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vmladavat.s8" } } */
+
+int32_t
+foo1 (int32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p)
+{
+ return vmladavaq_p (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vmladavat.s8" } } */
+/* { dg-final { scan-assembler "vmladavat.s8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u16.c
new file mode 100644
index 00000000000..8fe3ade9be2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u16.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32_t
+foo (uint32_t a, uint16x8_t b, uint16x8_t c, mve_pred16_t p)
+{
+ return vmladavaq_p_u16 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vmladavat.u16" } } */
+
+uint32_t
+foo1 (uint32_t a, uint16x8_t b, uint16x8_t c, mve_pred16_t p)
+{
+ return vmladavaq_p (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vmladavat.u16" } } */
+/* { dg-final { scan-assembler "vmladavat.u16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u32.c
new file mode 100644
index 00000000000..924322ee29d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u32.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32_t
+foo (uint32_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p)
+{
+ return vmladavaq_p_u32 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vmladavat.u32" } } */
+
+uint32_t
+foo1 (uint32_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p)
+{
+ return vmladavaq_p (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vmladavat.u32" } } */
+/* { dg-final { scan-assembler "vmladavat.u32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u8.c
new file mode 100644
index 00000000000..6e44d375f62
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u8.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32_t
+foo (uint32_t a, uint8x16_t b, uint8x16_t c, mve_pred16_t p)
+{
+ return vmladavaq_p_u8 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vmladavat.u8" } } */
+
+uint32_t
+foo1 (uint32_t a, uint8x16_t b, uint8x16_t c, mve_pred16_t p)
+{
+ return vmladavaq_p (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vmladavat.u8" } } */
+/* { dg-final { scan-assembler "vmladavat.u8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s16.c
new file mode 100644
index 00000000000..5ddefa91da9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s16.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32_t
+foo (int32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
+{
+ return vmladavaxq_p_s16 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vmladavaxt.s16" } } */
+
+int32_t
+foo1 (int32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
+{
+ return vmladavaxq_p (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vmladavaxt.s16" } } */
+/* { dg-final { scan-assembler "vmladavaxt.s16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s32.c
new file mode 100644
index 00000000000..f25f764284e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s32.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32_t
+foo (int32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
+{
+ return vmladavaxq_p_s32 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vmladavaxt.s32" } } */
+
+int32_t
+foo1 (int32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
+{
+ return vmladavaxq_p (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vmladavaxt.s32" } } */
+/* { dg-final { scan-assembler "vmladavaxt.s32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s8.c
new file mode 100644
index 00000000000..3ea63d64981
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s8.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32_t
+foo (int32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p)
+{
+ return vmladavaxq_p_s8 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vmladavaxt.s8" } } */
+
+int32_t
+foo1 (int32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p)
+{
+ return vmladavaxq_p (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vmladavaxt.s8" } } */
+/* { dg-final { scan-assembler "vmladavaxt.s8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c
new file mode 100644
index 00000000000..01b73b8417b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p)
+{
+ return vmlaq_m_n_s16 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmlat.s16" } } */
+
+int16x8_t
+foo1 (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p)
+{
+ return vmlaq_m (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmlat.s16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c
new file mode 100644
index 00000000000..c800e7b2866
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p)
+{
+ return vmlaq_m_n_s32 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmlat.s32" } } */
+
+int32x4_t
+foo1 (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p)
+{
+ return vmlaq_m (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmlat.s32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c
new file mode 100644
index 00000000000..8fb6c70bd0e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p)
+{
+ return vmlaq_m_n_s8 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmlat.s8" } } */
+
+int8x16_t
+foo1 (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p)
+{
+ return vmlaq_m (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmlat.s8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c
new file mode 100644
index 00000000000..9ec669aae52
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t a, uint16x8_t b, uint16_t c, mve_pred16_t p)
+{
+ return vmlaq_m_n_u16 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmlat.u16" } } */
+
+uint16x8_t
+foo1 (uint16x8_t a, uint16x8_t b, uint16_t c, mve_pred16_t p)
+{
+ return vmlaq_m (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmlat.u16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c
new file mode 100644
index 00000000000..2809abd93e9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint32x4_t a, uint32x4_t b, uint32_t c, mve_pred16_t p)
+{
+ return vmlaq_m_n_u32 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmlat.u32" } } */
+
+uint32x4_t
+foo1 (uint32x4_t a, uint32x4_t b, uint32_t c, mve_pred16_t p)
+{
+ return vmlaq_m (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmlat.u32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c
new file mode 100644
index 00000000000..a662b26da33
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint8x16_t
+foo (uint8x16_t a, uint8x16_t b, uint8_t c, mve_pred16_t p)
+{
+ return vmlaq_m_n_u8 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmlat.u8" } } */
+
+uint8x16_t
+foo1 (uint8x16_t a, uint8x16_t b, uint8_t c, mve_pred16_t p)
+{
+ return vmlaq_m (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmlat.u8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c
new file mode 100644
index 00000000000..bf2209d0bbf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p)
+{
+ return vmlasq_m_n_s16 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmlast.s16" } } */
+
+int16x8_t
+foo1 (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p)
+{
+ return vmlasq_m (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmlast.s16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c
new file mode 100644
index 00000000000..014f571649b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p)
+{
+ return vmlasq_m_n_s32 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmlast.s32" } } */
+
+int32x4_t
+foo1 (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p)
+{
+ return vmlasq_m (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmlast.s32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c
new file mode 100644
index 00000000000..a347adcd6fc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p)
+{
+ return vmlasq_m_n_s8 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmlast.s8" } } */
+
+int8x16_t
+foo1 (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p)
+{
+ return vmlasq_m (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmlast.s8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c
new file mode 100644
index 00000000000..c0e3a26a7af
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t a, uint16x8_t b, uint16_t c, mve_pred16_t p)
+{
+ return vmlasq_m_n_u16 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmlast.u16" } } */
+
+uint16x8_t
+foo1 (uint16x8_t a, uint16x8_t b, uint16_t c, mve_pred16_t p)
+{
+ return vmlasq_m (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmlast.u16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u32.c
new file mode 100644
index 00000000000..c74df5b4041
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint32x4_t a, uint32x4_t b, uint32_t c, mve_pred16_t p)
+{
+ return vmlasq_m_n_u32 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmlast.u32" } } */
+
+uint32x4_t
+foo1 (uint32x4_t a, uint32x4_t b, uint32_t c, mve_pred16_t p)
+{
+ return vmlasq_m (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmlast.u32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c
new file mode 100644
index 00000000000..3ca4a4b0e54
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint8x16_t
+foo (uint8x16_t a, uint8x16_t b, uint8_t c, mve_pred16_t p)
+{
+ return vmlasq_m_n_u8 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmlast.u8" } } */
+
+uint8x16_t
+foo1 (uint8x16_t a, uint8x16_t b, uint8_t c, mve_pred16_t p)
+{
+ return vmlasq_m (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmlast.u8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s16.c
new file mode 100644
index 00000000000..8ef9665e39d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s16.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32_t
+foo (int32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
+{
+ return vmlsdavaq_p_s16 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vmlsdavat.s16" } } */
+
+int32_t
+foo1 (int32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
+{
+ return vmlsdavaq_p (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vmlsdavat.s16" } } */
+/* { dg-final { scan-assembler "vmlsdavat.s16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s32.c
new file mode 100644
index 00000000000..40326c882e5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s32.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32_t
+foo (int32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
+{
+ return vmlsdavaq_p_s32 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vmlsdavat.s32" } } */
+
+int32_t
+foo1 (int32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
+{
+ return vmlsdavaq_p (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vmlsdavat.s32" } } */
+/* { dg-final { scan-assembler "vmlsdavat.s32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c
new file mode 100644
index 00000000000..5e035a3d02a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32_t
+foo (int32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p)
+{
+ return vmlsdavaq_p_s8 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vmlsdavat.s8" } } */
+
+int32_t
+foo1 (int32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p)
+{
+ return vmlsdavaq_p (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vmlsdavat.s8" } } */
+/* { dg-final { scan-assembler "vmlsdavat.s8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s16.c
new file mode 100644
index 00000000000..a1f4fe72fa4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s16.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32_t
+foo (int32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
+{
+ return vmlsdavaxq_p_s16 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vmlsdavaxt.s16" } } */
+
+int32_t
+foo1 (int32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
+{
+ return vmlsdavaxq_p (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vmlsdavaxt.s16" } } */
+/* { dg-final { scan-assembler "vmlsdavaxt.s16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s32.c
new file mode 100644
index 00000000000..c659aa7fcc0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s32.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32_t
+foo (int32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
+{
+ return vmlsdavaxq_p_s32 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vmlsdavaxt.s32" } } */
+
+int32_t
+foo1 (int32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
+{
+ return vmlsdavaxq_p (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vmlsdavaxt.s32" } } */
+/* { dg-final { scan-assembler "vmlsdavaxt.s32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s8.c
new file mode 100644
index 00000000000..462c04cb4b1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s8.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32_t
+foo (int32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p)
+{
+ return vmlsdavaxq_p_s8 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vmlsdavaxt.s8" } } */
+
+int32_t
+foo1 (int32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p)
+{
+ return vmlsdavaxq_p (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vmlsdavaxt.s8" } } */
+/* { dg-final { scan-assembler "vmlsdavaxt.s8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s16.c
new file mode 100644
index 00000000000..e73de9b2113
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vmulhq_m_s16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmulht.s16" } } */
+
+int16x8_t
+foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vmulhq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmulht.s16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s32.c
new file mode 100644
index 00000000000..21fa61f9da4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vmulhq_m_s32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmulht.s32" } } */
+
+int32x4_t
+foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vmulhq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmulht.s32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s8.c
new file mode 100644
index 00000000000..e789775792e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vmulhq_m_s8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmulht.s8" } } */
+
+int8x16_t
+foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vmulhq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmulht.s8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u16.c
new file mode 100644
index 00000000000..0b6dba78092
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+ return vmulhq_m_u16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmulht.u16" } } */
+
+uint16x8_t
+foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+ return vmulhq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmulht.u16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u32.c
new file mode 100644
index 00000000000..265212a4c41
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+{
+ return vmulhq_m_u32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmulht.u32" } } */
+
+uint32x4_t
+foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+{
+ return vmulhq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmulht.u32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u8.c
new file mode 100644
index 00000000000..5212df1f70d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint8x16_t
+foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+{
+ return vmulhq_m_u8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmulht.u8" } } */
+
+uint8x16_t
+foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+{
+ return vmulhq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmulht.u8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s16.c
new file mode 100644
index 00000000000..d1548b245cf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vmullbq_int_m_s16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmullbt.s16" } } */
+
+int32x4_t
+foo1 (int32x4_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vmullbq_int_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmullbt.s16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s32.c
new file mode 100644
index 00000000000..8ae8963b935
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int64x2_t
+foo (int64x2_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vmullbq_int_m_s32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmullbt.s32" } } */
+
+int64x2_t
+foo1 (int64x2_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vmullbq_int_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmullbt.s32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s8.c
new file mode 100644
index 00000000000..a5959c2b344
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vmullbq_int_m_s8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmullbt.s8" } } */
+
+int16x8_t
+foo1 (int16x8_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vmullbq_int_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmullbt.s8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u16.c
new file mode 100644
index 00000000000..2fb72175639
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint32x4_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+ return vmullbq_int_m_u16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmullbt.u16" } } */
+
+uint32x4_t
+foo1 (uint32x4_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+ return vmullbq_int_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmullbt.u16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u32.c
new file mode 100644
index 00000000000..2ba1bfc0368
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint64x2_t
+foo (uint64x2_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+{
+ return vmullbq_int_m_u32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmullbt.u32" } } */
+
+uint64x2_t
+foo1 (uint64x2_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+{
+ return vmullbq_int_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmullbt.u32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u8.c
new file mode 100644
index 00000000000..fa15fd2d97e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+{
+ return vmullbq_int_m_u8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmullbt.u8" } } */
+
+uint16x8_t
+foo1 (uint16x8_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+{
+ return vmullbq_int_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmullbt.u8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s16.c
new file mode 100644
index 00000000000..8c602dce7b8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vmulltq_int_m_s16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmulltt.s16" } } */
+
+int32x4_t
+foo1 (int32x4_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vmulltq_int_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmulltt.s16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s32.c
new file mode 100644
index 00000000000..a5a3e8afc02
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int64x2_t
+foo (int64x2_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vmulltq_int_m_s32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmulltt.s32" } } */
+
+int64x2_t
+foo1 (int64x2_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vmulltq_int_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmulltt.s32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s8.c
new file mode 100644
index 00000000000..3dd90ba963f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vmulltq_int_m_s8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmulltt.s8" } } */
+
+int16x8_t
+foo1 (int16x8_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vmulltq_int_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmulltt.s8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u16.c
new file mode 100644
index 00000000000..9a8d7664967
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint32x4_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+ return vmulltq_int_m_u16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmulltt.u16" } } */
+
+uint32x4_t
+foo1 (uint32x4_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+ return vmulltq_int_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmulltt.u16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u32.c
new file mode 100644
index 00000000000..0f072e77cc9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint64x2_t
+foo (uint64x2_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+{
+ return vmulltq_int_m_u32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmulltt.u32" } } */
+
+uint64x2_t
+foo1 (uint64x2_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+{
+ return vmulltq_int_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmulltt.u32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u8.c
new file mode 100644
index 00000000000..20c067b305b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+{
+ return vmulltq_int_m_u8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmulltt.u8" } } */
+
+uint16x8_t
+foo1 (uint16x8_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+{
+ return vmulltq_int_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmulltt.u8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c
new file mode 100644
index 00000000000..5c73b8b757e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
+{
+ return vmulq_m_n_s16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmult.i16" } } */
+
+int16x8_t
+foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
+{
+ return vmulq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmult.i16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c
new file mode 100644
index 00000000000..8cfa1b83efb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
+{
+ return vmulq_m_n_s32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmult.i32" } } */
+
+int32x4_t
+foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
+{
+ return vmulq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmult.i32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c
new file mode 100644
index 00000000000..82492dd42ae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
+{
+ return vmulq_m_n_s8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmult.i8" } } */
+
+int8x16_t
+foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
+{
+ return vmulq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmult.i8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c
new file mode 100644
index 00000000000..9e2e4839c87
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p)
+{
+ return vmulq_m_n_u16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmult.i16" } } */
+
+uint16x8_t
+foo1 (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p)
+{
+ return vmulq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmult.i16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c
new file mode 100644
index 00000000000..4aced386142
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p)
+{
+ return vmulq_m_n_u32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmult.i32" } } */
+
+uint32x4_t
+foo1 (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p)
+{
+ return vmulq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmult.i32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c
new file mode 100644
index 00000000000..7afcd477214
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint8x16_t
+foo (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p)
+{
+ return vmulq_m_n_u8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmult.i8" } } */
+
+uint8x16_t
+foo1 (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p)
+{
+ return vmulq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmult.i8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s16.c
new file mode 100644
index 00000000000..1b32d9bf07c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vmulq_m_s16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmult.i16" } } */
+
+int16x8_t
+foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vmulq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmult.i16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s32.c
new file mode 100644
index 00000000000..cb4e54ba645
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vmulq_m_s32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmult.i32" } } */
+
+int32x4_t
+foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vmulq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmult.i32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s8.c
new file mode 100644
index 00000000000..90c8d59499f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vmulq_m_s8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmult.i8" } } */
+
+int8x16_t
+foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vmulq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmult.i8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u16.c
new file mode 100644
index 00000000000..7f10e893736
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+ return vmulq_m_u16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmult.i16" } } */
+
+uint16x8_t
+foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+ return vmulq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmult.i16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u32.c
new file mode 100644
index 00000000000..521658cba45
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+{
+ return vmulq_m_u32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmult.i32" } } */
+
+uint32x4_t
+foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+{
+ return vmulq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmult.i32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u8.c
new file mode 100644
index 00000000000..d9af6fa2d58
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint8x16_t
+foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+{
+ return vmulq_m_u8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmult.i8" } } */
+
+uint8x16_t
+foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+{
+ return vmulq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmult.i8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s16.c
new file mode 100644
index 00000000000..bc2c3b8f4e0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vornq_m_s16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vornt" } } */
+
+int16x8_t
+foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vornq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vornt" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s32.c
new file mode 100644
index 00000000000..2c50ea2eb04
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vornq_m_s32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vornt" } } */
+
+int32x4_t
+foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vornq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vornt" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s8.c
new file mode 100644
index 00000000000..20bf2ebd741
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vornq_m_s8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vornt" } } */
+
+int8x16_t
+foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vornq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vornt" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u16.c
new file mode 100644
index 00000000000..d3e68c621ee
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+ return vornq_m_u16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vornt" } } */
+
+uint16x8_t
+foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+ return vornq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vornt" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u32.c
new file mode 100644
index 00000000000..594822e5779
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+{
+ return vornq_m_u32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vornt" } } */
+
+uint32x4_t
+foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+{
+ return vornq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vornt" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u8.c
new file mode 100644
index 00000000000..fcab2ced2c1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint8x16_t
+foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+{
+ return vornq_m_u8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vornt" } } */
+
+uint8x16_t
+foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+{
+ return vornq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vornt" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s16.c
new file mode 100644
index 00000000000..cd55980dd47
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vorrq_m_s16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vorrt" } } */
+
+int16x8_t
+foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vorrq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vorrt" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s32.c
new file mode 100644
index 00000000000..6f7ce5589b9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vorrq_m_s32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vorrt" } } */
+
+int32x4_t
+foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vorrq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vorrt" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s8.c
new file mode 100644
index 00000000000..ed99e5109a3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vorrq_m_s8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vorrt" } } */
+
+int8x16_t
+foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vorrq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vorrt" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u16.c
new file mode 100644
index 00000000000..e48050a8c66
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+ return vorrq_m_u16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vorrt" } } */
+
+uint16x8_t
+foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+ return vorrq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vorrt" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u32.c
new file mode 100644
index 00000000000..611e8156407
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+{
+ return vorrq_m_u32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vorrt" } } */
+
+uint32x4_t
+foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+{
+ return vorrq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vorrt" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u8.c
new file mode 100644
index 00000000000..e2d49f523d3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint8x16_t
+foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+{
+ return vorrq_m_u8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vorrt" } } */
+
+uint8x16_t
+foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+{
+ return vorrq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vorrt" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c
new file mode 100644
index 00000000000..367bf20127e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
+{
+ return vqaddq_m_n_s16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqaddt.s16" } } */
+
+int16x8_t
+foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
+{
+ return vqaddq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqaddt.s16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c
new file mode 100644
index 00000000000..3082db02be2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
+{
+ return vqaddq_m_n_s32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqaddt.s32" } } */
+
+int32x4_t
+foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
+{
+ return vqaddq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqaddt.s32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c
new file mode 100644
index 00000000000..12e65734c36
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
+{
+ return vqaddq_m_n_s8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqaddt.s8" } } */
+
+int8x16_t
+foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
+{
+ return vqaddq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqaddt.s8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c
new file mode 100644
index 00000000000..1ca7a1cd63f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p)
+{
+ return vqaddq_m_n_u16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqaddt.u16" } } */
+
+uint16x8_t
+foo1 (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p)
+{
+ return vqaddq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqaddt.u16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c
new file mode 100644
index 00000000000..b27a7d6a668
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p)
+{
+ return vqaddq_m_n_u32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqaddt.u32" } } */
+
+uint32x4_t
+foo1 (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p)
+{
+ return vqaddq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqaddt.u32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c
new file mode 100644
index 00000000000..434125ed715
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint8x16_t
+foo (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p)
+{
+ return vqaddq_m_n_u8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqaddt.u8" } } */
+
+uint8x16_t
+foo1 (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p)
+{
+ return vqaddq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqaddt.u8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c
new file mode 100644
index 00000000000..de13f243637
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vqaddq_m_s16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqaddt.s16" } } */
+
+int16x8_t
+foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vqaddq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqaddt.s16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c
new file mode 100644
index 00000000000..57044b2deba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vqaddq_m_s32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqaddt.s32" } } */
+
+int32x4_t
+foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vqaddq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqaddt.s32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c
new file mode 100644
index 00000000000..6fa2718f130
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vqaddq_m_s8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqaddt.s8" } } */
+
+int8x16_t
+foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vqaddq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqaddt.s8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c
new file mode 100644
index 00000000000..9f304eeb191
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+ return vqaddq_m_u16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqaddt.u16" } } */
+
+uint16x8_t
+foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+ return vqaddq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqaddt.u16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c
new file mode 100644
index 00000000000..3fd179fe6cd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+{
+ return vqaddq_m_u32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqaddt.u32" } } */
+
+uint32x4_t
+foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+{
+ return vqaddq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqaddt.u32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c
new file mode 100644
index 00000000000..136cdb4d2e2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint8x16_t
+foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+{
+ return vqaddq_m_u8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqaddt.u8" } } */
+
+uint8x16_t
+foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+{
+ return vqaddq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqaddt.u8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s16.c
new file mode 100644
index 00000000000..80616799be4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vqdmladhq_m_s16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmladht.s16" } } */
+
+int16x8_t
+foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vqdmladhq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmladht.s16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s32.c
new file mode 100644
index 00000000000..e6ee9a70a5e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vqdmladhq_m_s32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmladht.s32" } } */
+
+int32x4_t
+foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vqdmladhq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmladht.s32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s8.c
new file mode 100644
index 00000000000..bf4ff90f9d6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vqdmladhq_m_s8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmladht.s8" } } */
+
+int8x16_t
+foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vqdmladhq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmladht.s8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s16.c
new file mode 100644
index 00000000000..d45c6e9e048
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vqdmladhxq_m_s16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmladhxt.s16" } } */
+
+int16x8_t
+foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vqdmladhxq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmladhxt.s16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s32.c
new file mode 100644
index 00000000000..daea1cfce70
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vqdmladhxq_m_s32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmladhxt.s32" } } */
+
+int32x4_t
+foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vqdmladhxq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmladhxt.s32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s8.c
new file mode 100644
index 00000000000..138cfd5b0da
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vqdmladhxq_m_s8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmladhxt.s8" } } */
+
+int8x16_t
+foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vqdmladhxq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmladhxt.s8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s16.c
new file mode 100644
index 00000000000..91e88898fb9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p)
+{
+ return vqdmlahq_m_n_s16 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmlaht.s16" } } */
+
+int16x8_t
+foo1 (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p)
+{
+ return vqdmlahq_m (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmlaht.s16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s32.c
new file mode 100644
index 00000000000..2e0854763f3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p)
+{
+ return vqdmlahq_m_n_s32 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmlaht.s32" } } */
+
+int32x4_t
+foo1 (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p)
+{
+ return vqdmlahq_m (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmlaht.s32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s8.c
new file mode 100644
index 00000000000..430a9cf50c6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p)
+{
+ return vqdmlahq_m_n_s8 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmlaht.s8" } } */
+
+int8x16_t
+foo1 (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p)
+{
+ return vqdmlahq_m (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmlaht.s8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s16.c
new file mode 100644
index 00000000000..a79b13d2d85
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vqdmlsdhq_m_s16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmlsdht.s16" } } */
+
+int16x8_t
+foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vqdmlsdhq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmlsdht.s16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s32.c
new file mode 100644
index 00000000000..c15b74a9d9c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vqdmlsdhq_m_s32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmlsdht.s32" } } */
+
+int32x4_t
+foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vqdmlsdhq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmlsdht.s32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s8.c
new file mode 100644
index 00000000000..571962d8f60
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vqdmlsdhq_m_s8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmlsdht.s8" } } */
+
+int8x16_t
+foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vqdmlsdhq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmlsdht.s8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s16.c
new file mode 100644
index 00000000000..47b95dd5fe4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vqdmlsdhxq_m_s16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmlsdhxt.s16" } } */
+
+int16x8_t
+foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vqdmlsdhxq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmlsdhxt.s16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s32.c
new file mode 100644
index 00000000000..6e20e5bee8f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vqdmlsdhxq_m_s32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmlsdhxt.s32" } } */
+
+int32x4_t
+foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vqdmlsdhxq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmlsdhxt.s32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s8.c
new file mode 100644
index 00000000000..297db079cbb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vqdmlsdhxq_m_s8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmlsdhxt.s8" } } */
+
+int8x16_t
+foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vqdmlsdhxq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmlsdhxt.s8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s16.c
new file mode 100644
index 00000000000..747fd3c08c9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
+{
+ return vqdmulhq_m_n_s16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmulht.s16" } } */
+
+int16x8_t
+foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
+{
+ return vqdmulhq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmulht.s16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s32.c
new file mode 100644
index 00000000000..b50f91401ca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
+{
+ return vqdmulhq_m_n_s32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmulht.s32" } } */
+
+int32x4_t
+foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
+{
+ return vqdmulhq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmulht.s32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s8.c
new file mode 100644
index 00000000000..1f4dc63dba5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
+{
+ return vqdmulhq_m_n_s8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmulht.s8" } } */
+
+int8x16_t
+foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
+{
+ return vqdmulhq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmulht.s8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s16.c
new file mode 100644
index 00000000000..59e6b18f981
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vqdmulhq_m_s16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmulht.s16" } } */
+
+int16x8_t
+foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vqdmulhq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmulht.s16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s32.c
new file mode 100644
index 00000000000..b806a660de3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vqdmulhq_m_s32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmulht.s32" } } */
+
+int32x4_t
+foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vqdmulhq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmulht.s32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s8.c
new file mode 100644
index 00000000000..3f8fcf6dde0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vqdmulhq_m_s8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmulht.s8" } } */
+
+int8x16_t
+foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vqdmulhq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmulht.s8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s16.c
new file mode 100644
index 00000000000..ba1b44ddcd8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vqrdmladhq_m_s16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrdmladht.s16" } } */
+
+int16x8_t
+foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vqrdmladhq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrdmladht.s16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s32.c
new file mode 100644
index 00000000000..8503dfc64b1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vqrdmladhq_m_s32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrdmladht.s32" } } */
+
+int32x4_t
+foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vqrdmladhq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrdmladht.s32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s8.c
new file mode 100644
index 00000000000..f13b6251de8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vqrdmladhq_m_s8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrdmladht.s8" } } */
+
+int8x16_t
+foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vqrdmladhq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrdmladht.s8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s16.c
new file mode 100644
index 00000000000..854eac4250e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vqrdmladhxq_m_s16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrdmladhxt.s16" } } */
+
+int16x8_t
+foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vqrdmladhxq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrdmladhxt.s16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s32.c
new file mode 100644
index 00000000000..b96ca346a39
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vqrdmladhxq_m_s32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrdmladhxt.s32" } } */
+
+int32x4_t
+foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vqrdmladhxq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrdmladhxt.s32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s8.c
new file mode 100644
index 00000000000..af480b0a3e2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vqrdmladhxq_m_s8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrdmladhxt.s8" } } */
+
+int8x16_t
+foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vqrdmladhxq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrdmladhxt.s8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c
new file mode 100644
index 00000000000..b9cd42e3548
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p)
+{
+ return vqrdmlahq_m_n_s16 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrdmlaht.s16" } } */
+
+int16x8_t
+foo1 (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p)
+{
+ return vqrdmlahq_m (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrdmlaht.s16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c
new file mode 100644
index 00000000000..cf14605d2e0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p)
+{
+ return vqrdmlahq_m_n_s32 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrdmlaht.s32" } } */
+
+int32x4_t
+foo1 (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p)
+{
+ return vqrdmlahq_m (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrdmlaht.s32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c
new file mode 100644
index 00000000000..4ac58f2f26e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p)
+{
+ return vqrdmlahq_m_n_s8 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrdmlaht.s8" } } */
+
+int8x16_t
+foo1 (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p)
+{
+ return vqrdmlahq_m (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrdmlaht.s8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c
new file mode 100644
index 00000000000..f62974e98e3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p)
+{
+ return vqrdmlashq_m_n_s16 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrdmlasht.s16" } } */
+
+int16x8_t
+foo1 (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p)
+{
+ return vqrdmlashq_m (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrdmlasht.s16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c
new file mode 100644
index 00000000000..2250d74be4d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p)
+{
+ return vqrdmlashq_m_n_s32 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrdmlasht.s32" } } */
+
+int32x4_t
+foo1 (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p)
+{
+ return vqrdmlashq_m (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrdmlasht.s32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c
new file mode 100644
index 00000000000..f85f30211dd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p)
+{
+ return vqrdmlashq_m_n_s8 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrdmlasht.s8" } } */
+
+int8x16_t
+foo1 (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p)
+{
+ return vqrdmlashq_m (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrdmlasht.s8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s16.c
new file mode 100644
index 00000000000..0aae23ff294
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vqrdmlsdhq_m_s16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrdmlsdht.s16" } } */
+
+int16x8_t
+foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vqrdmlsdhq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrdmlsdht.s16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s32.c
new file mode 100644
index 00000000000..3490312495a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vqrdmlsdhq_m_s32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrdmlsdht.s32" } } */
+
+int32x4_t
+foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vqrdmlsdhq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrdmlsdht.s32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s8.c
new file mode 100644
index 00000000000..4fef001bdcc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vqrdmlsdhq_m_s8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrdmlsdht.s8" } } */
+
+int8x16_t
+foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vqrdmlsdhq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrdmlsdht.s8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c
new file mode 100644
index 00000000000..ac86aaeedee
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vqrdmlsdhxq_m_s16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrdmlsdhxt.s16" } } */
+
+int16x8_t
+foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vqrdmlsdhxq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrdmlsdhxt.s16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c
new file mode 100644
index 00000000000..7dd2d425653
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vqrdmlsdhxq_m_s32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrdmlsdhxt.s32" } } */
+
+int32x4_t
+foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vqrdmlsdhxq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrdmlsdhxt.s32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c
new file mode 100644
index 00000000000..da2d78ec1e6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vqrdmlsdhxq_m_s8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrdmlsdhxt.s8" } } */
+
+int8x16_t
+foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vqrdmlsdhxq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrdmlsdhxt.s8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c
new file mode 100644
index 00000000000..ebea67e1139
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
+{
+ return vqrdmulhq_m_n_s16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrdmulht.s16" } } */
+
+int16x8_t
+foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
+{
+ return vqrdmulhq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrdmulht.s16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c
new file mode 100644
index 00000000000..2ae4b9aaac6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
+{
+ return vqrdmulhq_m_n_s32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrdmulht.s32" } } */
+
+int32x4_t
+foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
+{
+ return vqrdmulhq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrdmulht.s32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c
new file mode 100644
index 00000000000..f44778e7f46
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
+{
+ return vqrdmulhq_m_n_s8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrdmulht.s8" } } */
+
+int8x16_t
+foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
+{
+ return vqrdmulhq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrdmulht.s8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s16.c
new file mode 100644
index 00000000000..9acdb2f6c88
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vqrdmulhq_m_s16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrdmulht.s16" } } */
+
+int16x8_t
+foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vqrdmulhq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrdmulht.s16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s32.c
new file mode 100644
index 00000000000..5b041f889a4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vqrdmulhq_m_s32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrdmulht.s32" } } */
+
+int32x4_t
+foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vqrdmulhq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrdmulht.s32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c
new file mode 100644
index 00000000000..bb339ee5289
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vqrdmulhq_m_s8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrdmulht.s8" } } */
+
+int8x16_t
+foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vqrdmulhq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrdmulht.s8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s16.c
new file mode 100644
index 00000000000..71391903b6e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vqrshlq_m_s16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrshlt.s16" } } */
+
+int16x8_t
+foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vqrshlq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrshlt.s16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s32.c
new file mode 100644
index 00000000000..3fd1b4662be
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vqrshlq_m_s32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrshlt.s32" } } */
+
+int32x4_t
+foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vqrshlq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrshlt.s32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s8.c
new file mode 100644
index 00000000000..f23f5c90e2e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vqrshlq_m_s8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrshlt.s8" } } */
+
+int8x16_t
+foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vqrshlq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrshlt.s8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u16.c
new file mode 100644
index 00000000000..2675da7c4c5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vqrshlq_m_u16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrshlt.u16" } } */
+
+uint16x8_t
+foo1 (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vqrshlq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrshlt.u16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u32.c
new file mode 100644
index 00000000000..3da5ec0ce67
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vqrshlq_m_u32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrshlt.u32" } } */
+
+uint32x4_t
+foo1 (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vqrshlq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrshlt.u32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u8.c
new file mode 100644
index 00000000000..2dd5be97d4b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint8x16_t
+foo (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vqrshlq_m_u8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrshlt.u8" } } */
+
+uint8x16_t
+foo1 (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vqrshlq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrshlt.u8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s16.c
new file mode 100644
index 00000000000..7077b944632
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
+{
+ return vqshlq_m_n_s16 (inactive, a, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqshlt.s16" } } */
+
+int16x8_t
+foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
+{
+ return vqshlq_m_n (inactive, a, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqshlt.s16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s32.c
new file mode 100644
index 00000000000..301e9d606d4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
+{
+ return vqshlq_m_n_s32 (inactive, a, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqshlt.s32" } } */
+
+int32x4_t
+foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
+{
+ return vqshlq_m_n (inactive, a, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqshlt.s32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s8.c
new file mode 100644
index 00000000000..1cb13d2108f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
+{
+ return vqshlq_m_n_s8 (inactive, a, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqshlt.s8" } } */
+
+int8x16_t
+foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
+{
+ return vqshlq_m_n (inactive, a, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqshlt.s8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u16.c
new file mode 100644
index 00000000000..5832a1ef312
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
+{
+ return vqshlq_m_n_u16 (inactive, a, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqshlt.u16" } } */
+
+uint16x8_t
+foo1 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
+{
+ return [...]
[diff truncated at 524288 bytes]
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2020-03-18 16:59 [gcc r10-7256] [ARM][GCC][2/4x]: MVE intrinsics with quaternary operands Kyrylo Tkachov
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