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* [gcc(refs/vendors/ibm/heads/perf)] i386: Use ix86_output_ssemov for DImode TYPE_SSEMOV
@ 2020-03-19 6:19 Jiu Fu Guo
0 siblings, 0 replies; only message in thread
From: Jiu Fu Guo @ 2020-03-19 6:19 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:824722e45f80b22e2f035a61300f494b2a10d6f4
commit 824722e45f80b22e2f035a61300f494b2a10d6f4
Author: H.J. Lu <hjl.tools@gmail.com>
Date: Sat Mar 14 16:06:55 2020 -0700
i386: Use ix86_output_ssemov for DImode TYPE_SSEMOV
There is no need to set mode attribute to XImode since ix86_output_ssemov
can properly encode xmm16-xmm31 registers with and without AVX512VL.
gcc/
PR target/89229
* config/i386/i386.md (*movdi_internal): Call ix86_output_ssemov
for TYPE_SSEMOV. Remove ext_sse_reg_operand and TARGET_AVX512VL
check.
gcc/testsuite/
PR target/89229
* gcc.target/i386/pr89229-5a.c: New test.
* gcc.target/i386/pr89229-5b.c: Likewise.
* gcc.target/i386/pr89229-5c.c: Likewise.
Diff:
---
gcc/ChangeLog | 7 +++++++
gcc/config/i386/i386.md | 31 ++----------------------------
gcc/testsuite/ChangeLog | 7 +++++++
gcc/testsuite/gcc.target/i386/pr89229-5a.c | 17 ++++++++++++++++
gcc/testsuite/gcc.target/i386/pr89229-5b.c | 6 ++++++
gcc/testsuite/gcc.target/i386/pr89229-5c.c | 7 +++++++
6 files changed, 46 insertions(+), 29 deletions(-)
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 0f79a7cfc20..91e9467e22e 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2020-03-14 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR target/89229
+ * config/i386/i386.md (*movdi_internal): Call ix86_output_ssemov
+ for TYPE_SSEMOV. Remove ext_sse_reg_operand and TARGET_AVX512VL
+ check.
+
2020-03-14 Jakub Jelinek <jakub@redhat.com>
* gimple-fold.c (gimple_fold_builtin_strncpy): Change
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 0f57f939cc3..6fa5db0a452 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -2054,31 +2054,7 @@
return standard_sse_constant_opcode (insn, operands);
case TYPE_SSEMOV:
- switch (get_attr_mode (insn))
- {
- case MODE_DI:
- /* Handle broken assemblers that require movd instead of movq. */
- if (!HAVE_AS_IX86_INTERUNIT_MOVQ
- && (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1])))
- return "%vmovd\t{%1, %0|%0, %1}";
- return "%vmovq\t{%1, %0|%0, %1}";
-
- case MODE_TI:
- /* Handle AVX512 registers set. */
- if (EXT_REX_SSE_REG_P (operands[0])
- || EXT_REX_SSE_REG_P (operands[1]))
- return "vmovdqa64\t{%1, %0|%0, %1}";
- return "%vmovdqa\t{%1, %0|%0, %1}";
-
- case MODE_V2SF:
- gcc_assert (!TARGET_AVX);
- return "movlps\t{%1, %0|%0, %1}";
- case MODE_V4SF:
- return "%vmovaps\t{%1, %0|%0, %1}";
-
- default:
- gcc_unreachable ();
- }
+ return ix86_output_ssemov (insn, operands);
case TYPE_SSECVT:
if (SSE_REG_P (operands[0]))
@@ -2164,10 +2140,7 @@
(cond [(eq_attr "alternative" "2")
(const_string "SI")
(eq_attr "alternative" "12,13")
- (cond [(ior (match_operand 0 "ext_sse_reg_operand")
- (match_operand 1 "ext_sse_reg_operand"))
- (const_string "TI")
- (match_test "TARGET_AVX")
+ (cond [(match_test "TARGET_AVX")
(const_string "TI")
(ior (not (match_test "TARGET_SSE2"))
(match_test "optimize_function_for_size_p (cfun)"))
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 0f84567e883..2e758849bde 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,10 @@
+2020-03-14 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR target/89229
+ * gcc.target/i386/pr89229-5a.c: New test.
+ * gcc.target/i386/pr89229-5b.c: Likewise.
+ * gcc.target/i386/pr89229-5c.c: Likewise.
+
2020-03-14 Segher Boessenkool <segher@kernel.crashing.org>
PR target/94176
diff --git a/gcc/testsuite/gcc.target/i386/pr89229-5a.c b/gcc/testsuite/gcc.target/i386/pr89229-5a.c
new file mode 100644
index 00000000000..cb9b071e873
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr89229-5a.c
@@ -0,0 +1,17 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -march=skylake-avx512 -mprefer-vector-width=512" } */
+
+extern long long i;
+
+long long
+foo1 (void)
+{
+ register long long xmm16 __asm ("xmm16") = i;
+ asm volatile ("" : "+v" (xmm16));
+ register long long xmm17 __asm ("xmm17") = xmm16;
+ asm volatile ("" : "+v" (xmm17));
+ return xmm17;
+}
+
+/* { dg-final { scan-assembler-times "vmovdqa64\[^\n\r]*xmm1\[67]\[^\n\r]*xmm1\[67]" 1 } } */
+/* { dg-final { scan-assembler-not "%zmm\[0-9\]+" } } */
diff --git a/gcc/testsuite/gcc.target/i386/pr89229-5b.c b/gcc/testsuite/gcc.target/i386/pr89229-5b.c
new file mode 100644
index 00000000000..261f2e12e8d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr89229-5b.c
@@ -0,0 +1,6 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -march=skylake-avx512 -mno-avx512vl" } */
+
+#include "pr89229-5a.c"
+
+/* { dg-final { scan-assembler-times "vmovdqa32\[^\n\r]*zmm1\[67]\[^\n\r]*zmm1\[67]" 1 } } */
diff --git a/gcc/testsuite/gcc.target/i386/pr89229-5c.c b/gcc/testsuite/gcc.target/i386/pr89229-5c.c
new file mode 100644
index 00000000000..5fe537f47cd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr89229-5c.c
@@ -0,0 +1,7 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -march=skylake-avx512 -mprefer-vector-width=512" } */
+
+#include "pr89229-5a.c"
+
+/* { dg-final { scan-assembler-times "vmovdqa64\[^\n\r]*xmm1\[67]\[^\n\r]*xmm1\[67]" 1 } } */
+/* { dg-final { scan-assembler-not "%zmm\[0-9\]+" } } */
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