public inbox for gcc-cvs@sourceware.org
help / color / mirror / Atom feed
* [gcc(refs/users/guojiufu/heads/personal-branch)] rs6000: Prefer VSX insns over VMX ones (part 1: perm and mrg)
@ 2020-06-10 3:19 Jiu Fu Guo
0 siblings, 0 replies; only message in thread
From: Jiu Fu Guo @ 2020-06-10 3:19 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:ee969a36d9887e1a3230fe3de2d398fd6c6dac49
commit ee969a36d9887e1a3230fe3de2d398fd6c6dac49
Author: Segher Boessenkool <segher@kernel.crashing.org>
Date: Fri May 29 21:32:41 2020 +0000
rs6000: Prefer VSX insns over VMX ones (part 1: perm and mrg)
There are various VSX insns that do the same job as (older) AltiVec
insns, just with a wider range of possible registers. Many patterns
for such insns have the "v" alternative before the "wa" alternative,
which makes the output less readable than possible (since vs32 is v0,
and most insns before or after this insn will be VSX as well).
This changes the define_insns for the mrg and perm machine instructions
to prefer the VSX form. No behaviour change. Only one testcase needed
a little adjustment as well.
2020-05-29 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/altivec.md (altivec_vmrghw_direct): Prefer VSX form.
(altivec_vmrglw_direct): Ditto.
(altivec_vperm_<mode>_direct): Ditto.
(altivec_vperm_v8hiv16qi): Ditto.
(*altivec_vperm_<mode>_uns_internal): Ditto.
(*altivec_vpermr_<mode>_internal): Ditto.
(vperm_v8hiv4si): Ditto.
(vperm_v16qiv8hi): Ditto.
gcc/testsuite/
* gcc.target/powerpc/vsx-vector-6.p9.c: Allow xxperm as perm as well.
Diff:
---
gcc/config/rs6000/altivec.md | 104 ++++++++++-----------
gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p9.c | 2 +-
2 files changed, 53 insertions(+), 53 deletions(-)
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 792ca4f488e..159f24ebc10 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -1216,14 +1216,14 @@
[(set_attr "type" "vecperm")])
(define_insn "altivec_vmrghw_direct"
- [(set (match_operand:V4SI 0 "register_operand" "=v,wa")
- (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v,wa")
- (match_operand:V4SI 2 "register_operand" "v,wa")]
+ [(set (match_operand:V4SI 0 "register_operand" "=wa,v")
+ (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "wa,v")
+ (match_operand:V4SI 2 "register_operand" "wa,v")]
UNSPEC_VMRGH_DIRECT))]
"TARGET_ALTIVEC"
"@
- vmrghw %0,%1,%2
- xxmrghw %x0,%x1,%x2"
+ xxmrghw %x0,%x1,%x2
+ vmrghw %0,%1,%2"
[(set_attr "type" "vecperm")])
(define_insn "*altivec_vmrghsf"
@@ -1364,14 +1364,14 @@
[(set_attr "type" "vecperm")])
(define_insn "altivec_vmrglw_direct"
- [(set (match_operand:V4SI 0 "register_operand" "=v,wa")
- (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v,wa")
- (match_operand:V4SI 2 "register_operand" "v,wa")]
+ [(set (match_operand:V4SI 0 "register_operand" "=wa,v")
+ (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "wa,v")
+ (match_operand:V4SI 2 "register_operand" "wa,v")]
UNSPEC_VMRGL_DIRECT))]
"TARGET_ALTIVEC"
"@
- vmrglw %0,%1,%2
- xxmrglw %x0,%x1,%x2"
+ xxmrglw %x0,%x1,%x2
+ vmrglw %0,%1,%2"
[(set_attr "type" "vecperm")])
(define_insn "*altivec_vmrglsf"
@@ -2193,30 +2193,30 @@
;; Slightly prefer vperm, since the target does not overlap the source
(define_insn "altivec_vperm_<mode>_direct"
- [(set (match_operand:VM 0 "register_operand" "=v,?wa")
- (unspec:VM [(match_operand:VM 1 "register_operand" "v,wa")
- (match_operand:VM 2 "register_operand" "v,0")
- (match_operand:V16QI 3 "register_operand" "v,wa")]
+ [(set (match_operand:VM 0 "register_operand" "=?wa,v")
+ (unspec:VM [(match_operand:VM 1 "register_operand" "wa,v")
+ (match_operand:VM 2 "register_operand" "0,v")
+ (match_operand:V16QI 3 "register_operand" "wa,v")]
UNSPEC_VPERM))]
"TARGET_ALTIVEC"
"@
- vperm %0,%1,%2,%3
- xxperm %x0,%x1,%x3"
+ xxperm %x0,%x1,%x3
+ vperm %0,%1,%2,%3"
[(set_attr "type" "vecperm")
- (set_attr "isa" "*,p9v")])
+ (set_attr "isa" "p9v,*")])
(define_insn "altivec_vperm_v8hiv16qi"
- [(set (match_operand:V16QI 0 "register_operand" "=v,?wa")
- (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v,wa")
- (match_operand:V8HI 2 "register_operand" "v,0")
- (match_operand:V16QI 3 "register_operand" "v,wa")]
+ [(set (match_operand:V16QI 0 "register_operand" "=?wa,v")
+ (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "wa,v")
+ (match_operand:V8HI 2 "register_operand" "0,v")
+ (match_operand:V16QI 3 "register_operand" "wa,v")]
UNSPEC_VPERM))]
"TARGET_ALTIVEC"
"@
- vperm %0,%1,%2,%3
- xxperm %x0,%x1,%x3"
+ xxperm %x0,%x1,%x3
+ vperm %0,%1,%2,%3"
[(set_attr "type" "vecperm")
- (set_attr "isa" "*,p9v")])
+ (set_attr "isa" "p9v,*")])
(define_expand "altivec_vperm_<mode>_uns"
[(set (match_operand:VM 0 "register_operand")
@@ -2234,17 +2234,17 @@
})
(define_insn "*altivec_vperm_<mode>_uns_internal"
- [(set (match_operand:VM 0 "register_operand" "=v,?wa")
- (unspec:VM [(match_operand:VM 1 "register_operand" "v,wa")
- (match_operand:VM 2 "register_operand" "v,0")
- (match_operand:V16QI 3 "register_operand" "v,wa")]
+ [(set (match_operand:VM 0 "register_operand" "=?wa,v")
+ (unspec:VM [(match_operand:VM 1 "register_operand" "wa,v")
+ (match_operand:VM 2 "register_operand" "0,v")
+ (match_operand:V16QI 3 "register_operand" "wa,v")]
UNSPEC_VPERM_UNS))]
"TARGET_ALTIVEC"
"@
- vperm %0,%1,%2,%3
- xxperm %x0,%x1,%x3"
+ xxperm %x0,%x1,%x3
+ vperm %0,%1,%2,%3"
[(set_attr "type" "vecperm")
- (set_attr "isa" "*,p9v")])
+ (set_attr "isa" "p9v,*")])
(define_expand "vec_permv16qi"
[(set (match_operand:V16QI 0 "register_operand")
@@ -2261,17 +2261,17 @@
})
(define_insn "*altivec_vpermr_<mode>_internal"
- [(set (match_operand:VM 0 "register_operand" "=v,?wa")
- (unspec:VM [(match_operand:VM 1 "register_operand" "v,wa")
- (match_operand:VM 2 "register_operand" "v,0")
- (match_operand:V16QI 3 "register_operand" "v,wa")]
+ [(set (match_operand:VM 0 "register_operand" "=?wa,v")
+ (unspec:VM [(match_operand:VM 1 "register_operand" "wa,v")
+ (match_operand:VM 2 "register_operand" "0,v")
+ (match_operand:V16QI 3 "register_operand" "wa,v")]
UNSPEC_VPERMR))]
"TARGET_P9_VECTOR"
"@
- vpermr %0,%1,%2,%3
- xxpermr %x0,%x1,%x3"
+ xxpermr %x0,%x1,%x3
+ vpermr %0,%1,%2,%3"
[(set_attr "type" "vecperm")
- (set_attr "isa" "*,p9v")])
+ (set_attr "isa" "p9v,*")])
(define_insn "altivec_vrfip" ; ceil
[(set (match_operand:V4SF 0 "register_operand" "=v")
@@ -3414,30 +3414,30 @@
"")
(define_insn "vperm_v8hiv4si"
- [(set (match_operand:V4SI 0 "register_operand" "=v,?wa")
- (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v,wa")
- (match_operand:V4SI 2 "register_operand" "v,0")
- (match_operand:V16QI 3 "register_operand" "v,wa")]
+ [(set (match_operand:V4SI 0 "register_operand" "=?wa,v")
+ (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "wa,v")
+ (match_operand:V4SI 2 "register_operand" "0,v")
+ (match_operand:V16QI 3 "register_operand" "wa,v")]
UNSPEC_VPERMSI))]
"TARGET_ALTIVEC"
"@
- vperm %0,%1,%2,%3
- xxperm %x0,%x1,%x3"
+ xxperm %x0,%x1,%x3
+ vperm %0,%1,%2,%3"
[(set_attr "type" "vecperm")
- (set_attr "isa" "*,p9v")])
+ (set_attr "isa" "p9v,*")])
(define_insn "vperm_v16qiv8hi"
- [(set (match_operand:V8HI 0 "register_operand" "=v,?wa")
- (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v,wa")
- (match_operand:V8HI 2 "register_operand" "v,0")
- (match_operand:V16QI 3 "register_operand" "v,wa")]
+ [(set (match_operand:V8HI 0 "register_operand" "=?wa,v")
+ (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "wa,v")
+ (match_operand:V8HI 2 "register_operand" "0,v")
+ (match_operand:V16QI 3 "register_operand" "wa,v")]
UNSPEC_VPERMHI))]
"TARGET_ALTIVEC"
"@
- vperm %0,%1,%2,%3
- xxperm %x0,%x1,%x3"
+ xxperm %x0,%x1,%x3
+ vperm %0,%1,%2,%3"
[(set_attr "type" "vecperm")
- (set_attr "isa" "*,p9v")])
+ (set_attr "isa" "p9v,*")])
(define_insn "xxeval"
[(set (match_operand:V2DI 0 "register_operand" "=wa")
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p9.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p9.c
index eabdf71a7be..43d2e855e0d 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p9.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p9.c
@@ -9,7 +9,7 @@
/* { dg-final { scan-assembler-times {\mvmaxub\M} 1 } } */
/* { dg-final { scan-assembler-times {\mvmsumshs\M} 1 } } */
/* { dg-final { scan-assembler-times {\mvmsumuhs\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mvpermr?\M} 1 } } */
+/* { dg-final { scan-assembler-times {\m(?:vpermr?|xxperm)\M} 1 } } */
/* { dg-final { scan-assembler-times {\mxvabsdp\M} 1 } } */
/* { dg-final { scan-assembler-times {\mxvadddp\M} 1 } } */
/* { dg-final { scan-assembler-times {\mxvcmpeqdp\M} 9 } } */
^ permalink raw reply [flat|nested] only message in thread
only message in thread, other threads:[~2020-06-10 3:19 UTC | newest]
Thread overview: (only message) (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-06-10 3:19 [gcc(refs/users/guojiufu/heads/personal-branch)] rs6000: Prefer VSX insns over VMX ones (part 1: perm and mrg) Jiu Fu Guo
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).