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* [gcc(refs/users/guojiufu/heads/personal-branch)] RISC-V: Unify the output asm pattern between gpr_save and gpr_restore pattern.
@ 2020-06-13 2:53 Jiu Fu Guo
0 siblings, 0 replies; only message in thread
From: Jiu Fu Guo @ 2020-06-13 2:53 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:dcf41a4e6033213f5e5f80da23080df961d83996
commit dcf41a4e6033213f5e5f80da23080df961d83996
Author: Kito Cheng <kito.cheng@sifive.com>
Date: Wed Jun 10 19:41:06 2020 -0700
RISC-V: Unify the output asm pattern between gpr_save and gpr_restore pattern.
gcc/ChangeLog:
* config/riscv/riscv-protos.h (riscv_output_gpr_save): Remove.
* config/riscv/riscv-sr.c (riscv_sr_match_prologue): Update
value.
* config/riscv/riscv.c (riscv_output_gpr_save): Remove.
* config/riscv/riscv.md (gpr_save): Update output asm pattern.
Diff:
---
gcc/config/riscv/riscv-protos.h | 1 -
gcc/config/riscv/riscv-sr.c | 2 +-
gcc/config/riscv/riscv.c | 16 +---------------
gcc/config/riscv/riscv.md | 2 +-
4 files changed, 3 insertions(+), 18 deletions(-)
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 9cda6a88879..358224af898 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -53,7 +53,6 @@ extern rtx riscv_subword (rtx, bool);
extern bool riscv_split_64bit_move_p (rtx, rtx);
extern void riscv_split_doubleword_move (rtx, rtx);
extern const char *riscv_output_move (rtx, rtx);
-extern const char *riscv_output_gpr_save (unsigned);
extern const char *riscv_output_return ();
#ifdef RTX_CODE
extern void riscv_expand_int_scc (rtx, enum rtx_code, rtx, rtx);
diff --git a/gcc/config/riscv/riscv-sr.c b/gcc/config/riscv/riscv-sr.c
index b8fe9d08fb0..9af50ef028e 100644
--- a/gcc/config/riscv/riscv-sr.c
+++ b/gcc/config/riscv/riscv-sr.c
@@ -115,7 +115,7 @@ riscv_sr_match_prologue (rtx_insn **body)
&& GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == UNSPEC_VOLATILE
&& (GET_CODE (XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 0))
== CONST_INT)
- && INTVAL (XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 0)) == 2)
+ && INTVAL (XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 0)) == 0)
return insn;
return NULL;
diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index c11ed060116..02ebf1945ea 100644
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -3951,20 +3951,6 @@ riscv_restore_reg (rtx reg, rtx mem)
RTX_FRAME_RELATED_P (insn) = 1;
}
-/* Return the code to invoke the GPR save routine. */
-
-const char *
-riscv_output_gpr_save (unsigned mask)
-{
- static char s[32];
- unsigned n = riscv_save_libcall_count (mask);
-
- ssize_t bytes = snprintf (s, sizeof (s), "call\tt0,__riscv_save_%u", n);
- gcc_assert ((size_t) bytes < sizeof (s));
-
- return s;
-}
-
/* For stack frames that can't be allocated with a single ADDI instruction,
compute the best value to initially allocate. It must at a minimum
allocate enough space to spill the callee-saved registers. If TARGET_RVC,
@@ -5199,7 +5185,7 @@ riscv_gen_gpr_save_insn (struct riscv_frame_info *frame)
RTVEC_ELT (vec, 0) =
gen_rtx_UNSPEC_VOLATILE (VOIDmode,
- gen_rtvec (1, GEN_INT (frame->mask)), UNSPECV_GPR_SAVE);
+ gen_rtvec (1, GEN_INT (count)), UNSPECV_GPR_SAVE);
for (int i = 1; i < veclen; ++i)
{
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index d9028c50b9a..36012ad1f77 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -2445,7 +2445,7 @@
[(unspec_volatile [(match_operand 0 "const_int_operand")]
UNSPECV_GPR_SAVE)])]
""
- { return riscv_output_gpr_save (INTVAL (operands[0])); })
+ "call\tt0,__riscv_save_%0")
(define_insn "gpr_restore"
[(unspec_volatile [(match_operand 0 "const_int_operand")] UNSPECV_GPR_RESTORE)]
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