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* [gcc r11-1302] RISC-V: Suppress warning for signed and unsigned integer comparison.
@ 2020-06-15 4:07 Kito Cheng
0 siblings, 0 replies; only message in thread
From: Kito Cheng @ 2020-06-15 4:07 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:82a3008e56c620008b4575a97e459e2769df54db
commit r11-1302-g82a3008e56c620008b4575a97e459e2769df54db
Author: Kito Cheng <kito.cheng@sifive.com>
Date: Mon Jun 15 11:51:13 2020 +0800
RISC-V: Suppress warning for signed and unsigned integer comparison.
gcc/ChangeLog:
* config/riscv/riscv.c (riscv_gen_gpr_save_insn): Change type to
unsigned for i.
(riscv_gpr_save_operation_p): Change type to unsigned for i and
len.
Diff:
---
gcc/config/riscv/riscv.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index 02ebf1945ea..328c0c823a3 100644
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -5187,7 +5187,7 @@ riscv_gen_gpr_save_insn (struct riscv_frame_info *frame)
gen_rtx_UNSPEC_VOLATILE (VOIDmode,
gen_rtvec (1, GEN_INT (count)), UNSPECV_GPR_SAVE);
- for (int i = 1; i < veclen; ++i)
+ for (unsigned i = 1; i < veclen; ++i)
{
unsigned regno = gpr_save_reg_order[i];
rtx reg = gen_rtx_REG (Pmode, regno);
@@ -5215,9 +5215,9 @@ riscv_gen_gpr_save_insn (struct riscv_frame_info *frame)
bool
riscv_gpr_save_operation_p (rtx op)
{
- HOST_WIDE_INT len = XVECLEN (op, 0);
+ unsigned len = XVECLEN (op, 0);
gcc_assert (len <= ARRAY_SIZE (gpr_save_reg_order));
- for (int i = 0; i < len; i++)
+ for (unsigned i = 0; i < len; i++)
{
rtx elt = XVECEXP (op, 0, i);
if (i == 0)
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