[gcc(refs/users/meissner/heads/work008-orig)] rs6000: Don't ICE when spilling an MMA accumulator

[Michael Meissner <meissner@gcc.gnu.org>]

https://gcc.gnu.org/g:9c376d1c166e7c8b10bba6f1675d2471ffe8447f

commit 9c376d1c166e7c8b10bba6f1675d2471ffe8447f
Author: Peter Bergner <bergner@linux.ibm.com>
Date:   Thu Aug 6 10:03:03 2020 -0500

    rs6000: Don't ICE when spilling an MMA accumulator
    
    When we spill an accumulator that has a known zero value, LRA will emit
    a new (set (reg:PXI ...) 0) insn, but it does not use the mma_xxsetaccz
    pattern to do it, leading to an unrecognized insn ICE.  The solution here
    is to move the xxsetaccz instruction into the movpxi pattern and have the
    xxsetaccz pattern call the move pattern.
    
    2020-08-06  Peter Bergner  <bergner@linux.ibm.com>
    
    gcc/
            PR target/96446
            * config/rs6000/mma.md (*movpxi): Add xxsetaccz generation.
            Disable split for zero constant source operand.
            (mma_xxsetaccz): Change to define_expand.  Call gen_movpxi.
    
    gcc/testsuite/
            PR target/96446
            * gcc.target/powerpc/pr96446.c: New test.

Diff:
---
 gcc/config/rs6000/mma.md                   | 22 ++++++++++++++--------
 gcc/testsuite/gcc.target/powerpc/pr96446.c | 16 ++++++++++++++++
 2 files changed, 30 insertions(+), 8 deletions(-)

diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md
index 15cacfb7fc1..a3fd28bdd0a 100644
--- a/gcc/config/rs6000/mma.md
+++ b/gcc/config/rs6000/mma.md
@@ -328,11 +328,15 @@
   [(set (match_operand:PXI 0 "nonimmediate_operand" "=d,m,d,d")
 	(match_operand:PXI 1 "input_operand" "m,d,d,O"))]
   "TARGET_MMA
-   && ((gpc_reg_operand (operands[0], PXImode)
-	&& !(CONST_INT_P (operands[1]) && INTVAL (operands[1]) == 0))
+   && (gpc_reg_operand (operands[0], PXImode)
        || gpc_reg_operand (operands[1], PXImode))"
-  "#"
-  "&& reload_completed"
+  "@
+   #
+   #
+   #
+   xxsetaccz %A0"
+  "&& reload_completed
+   && !(fpr_reg_operand (operands[0], PXImode) && operands[1] == const0_rtx)"
   [(const_int 0)]
 {
   rs6000_split_multireg_move (operands[0], operands[1]);
@@ -409,12 +413,14 @@
   "<acc> %A0"
   [(set_attr "type" "mma")])
 
-(define_insn "mma_xxsetaccz"
-  [(set (match_operand:PXI 0 "fpr_reg_operand" "=d")
+(define_expand "mma_xxsetaccz"
+  [(set (match_operand:PXI 0 "fpr_reg_operand")
 	(const_int 0))]
   "TARGET_MMA"
-  "xxsetaccz %A0"
-  [(set_attr "type" "mma")])
+{
+  emit_insn (gen_movpxi (operands[0], const0_rtx));
+  DONE;
+})
 
 (define_insn "mma_<vv>"
   [(set (match_operand:PXI 0 "fpr_reg_operand" "=&d")
diff --git a/gcc/testsuite/gcc.target/powerpc/pr96446.c b/gcc/testsuite/gcc.target/powerpc/pr96446.c
new file mode 100644
index 00000000000..2083bf4a76a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr96446.c
@@ -0,0 +1,16 @@
+/* PR target/96466 */
+/* { dg-do compile } */
+/* { dg-require-effective-target power10_ok } */
+/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
+
+/* Verify we do not ICE on the following.  */
+
+extern void bar0 (void);
+void
+foo0 (__vector_quad *dst)
+{
+  __vector_quad acc;
+  __builtin_mma_xxsetaccz (&acc);
+  bar0 ();
+  *dst = acc;
+}