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* [gcc/devel/autopar_devel] aarch64: add support for unpacked EOR, ORR and AND
@ 2020-08-22 21:42 Giuliano Belinassi
0 siblings, 0 replies; only message in thread
From: Giuliano Belinassi @ 2020-08-22 21:42 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:3a20f5a0812d6ab32d5a90e62882c91219375bec
commit 3a20f5a0812d6ab32d5a90e62882c91219375bec
Author: Joe Ramsay <joe.ramsay@arm.com>
Date: Fri May 29 08:44:37 2020 +0100
aarch64: add support for unpacked EOR, ORR and AND
Extended patterns for these instructions to support unpacked vectors.
BIC will have to wait, as there is not currently support for unpacked
NOT.
2020-05-29 Joe Ramsay <joe.ramsay@arm.com>
gcc/
* config/aarch64/aarch64-sve.md (<LOGICAL:optab><mode>3): Add support
for unpacked EOR, ORR, AND.
gcc/testsuite/
* gcc.target/aarch64/sve/load_const_offset_2.c: Force using packed
vectors.
* gcc.target/aarch64/sve/logical_unpacked_and_1.c: New test.
* gcc.target/aarch64/sve/logical_unpacked_and_2.c: New test.
* gcc.target/aarch64/sve/logical_unpacked_and_3.c: New test.
* gcc.target/aarch64/sve/logical_unpacked_and_4.c: New test.
* gcc.target/aarch64/sve/logical_unpacked_and_5.c: New test.
* gcc.target/aarch64/sve/logical_unpacked_and_6.c: New test.
* gcc.target/aarch64/sve/logical_unpacked_and_7.c: New test.
* gcc.target/aarch64/sve/logical_unpacked_eor_1.c: New test.
* gcc.target/aarch64/sve/logical_unpacked_eor_2.c: New test.
* gcc.target/aarch64/sve/logical_unpacked_eor_3.c: New test.
* gcc.target/aarch64/sve/logical_unpacked_eor_4.c: New test.
* gcc.target/aarch64/sve/logical_unpacked_eor_5.c: New test.
* gcc.target/aarch64/sve/logical_unpacked_eor_6.c: New test.
* gcc.target/aarch64/sve/logical_unpacked_eor_7.c: New test.
* gcc.target/aarch64/sve/logical_unpacked_orr_1.c: New test.
* gcc.target/aarch64/sve/logical_unpacked_orr_2.c: New test.
* gcc.target/aarch64/sve/logical_unpacked_orr_3.c: New test.
* gcc.target/aarch64/sve/logical_unpacked_orr_4.c: New test.
* gcc.target/aarch64/sve/logical_unpacked_orr_5.c: New test.
* gcc.target/aarch64/sve/logical_unpacked_orr_6.c: New test.
* gcc.target/aarch64/sve/logical_unpacked_orr_7.c: New test.
* gcc.target/aarch64/sve/scatter_store_6.c: Force using packed vectors.
* gcc.target/aarch64/sve/scatter_store_7.c: Force using packed vectors.
* gcc.target/aarch64/sve/strided_load_3.c: Force using packed vectors.
* gcc.target/aarch64/sve/strided_store_3.c: Force using packed vectors.
* gcc.target/aarch64/sve/unpack_signed_1.c: Force using packed vectors.
Diff:
---
gcc/config/aarch64/aarch64-sve.md | 8 ++++----
.../gcc.target/aarch64/sve/load_const_offset_2.c | 2 +-
.../gcc.target/aarch64/sve/logical_unpacked_and_1.c | 16 ++++++++++++++++
.../gcc.target/aarch64/sve/logical_unpacked_and_2.c | 17 +++++++++++++++++
.../gcc.target/aarch64/sve/logical_unpacked_and_3.c | 17 +++++++++++++++++
.../gcc.target/aarch64/sve/logical_unpacked_and_4.c | 17 +++++++++++++++++
.../gcc.target/aarch64/sve/logical_unpacked_and_5.c | 16 ++++++++++++++++
.../gcc.target/aarch64/sve/logical_unpacked_and_6.c | 17 +++++++++++++++++
.../gcc.target/aarch64/sve/logical_unpacked_and_7.c | 16 ++++++++++++++++
.../gcc.target/aarch64/sve/logical_unpacked_eor_1.c | 16 ++++++++++++++++
.../gcc.target/aarch64/sve/logical_unpacked_eor_2.c | 17 +++++++++++++++++
.../gcc.target/aarch64/sve/logical_unpacked_eor_3.c | 17 +++++++++++++++++
.../gcc.target/aarch64/sve/logical_unpacked_eor_4.c | 17 +++++++++++++++++
.../gcc.target/aarch64/sve/logical_unpacked_eor_5.c | 16 ++++++++++++++++
.../gcc.target/aarch64/sve/logical_unpacked_eor_6.c | 17 +++++++++++++++++
.../gcc.target/aarch64/sve/logical_unpacked_eor_7.c | 16 ++++++++++++++++
.../gcc.target/aarch64/sve/logical_unpacked_orr_1.c | 16 ++++++++++++++++
.../gcc.target/aarch64/sve/logical_unpacked_orr_2.c | 17 +++++++++++++++++
.../gcc.target/aarch64/sve/logical_unpacked_orr_3.c | 17 +++++++++++++++++
.../gcc.target/aarch64/sve/logical_unpacked_orr_4.c | 17 +++++++++++++++++
.../gcc.target/aarch64/sve/logical_unpacked_orr_5.c | 16 ++++++++++++++++
.../gcc.target/aarch64/sve/logical_unpacked_orr_6.c | 17 +++++++++++++++++
.../gcc.target/aarch64/sve/logical_unpacked_orr_7.c | 16 ++++++++++++++++
gcc/testsuite/gcc.target/aarch64/sve/scatter_store_6.c | 2 +-
gcc/testsuite/gcc.target/aarch64/sve/scatter_store_7.c | 2 +-
gcc/testsuite/gcc.target/aarch64/sve/strided_load_3.c | 2 +-
gcc/testsuite/gcc.target/aarch64/sve/strided_store_3.c | 2 +-
gcc/testsuite/gcc.target/aarch64/sve/unpack_signed_1.c | 2 +-
28 files changed, 358 insertions(+), 10 deletions(-)
diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md
index f7a08935af6..8f0944c2992 100644
--- a/gcc/config/aarch64/aarch64-sve.md
+++ b/gcc/config/aarch64/aarch64-sve.md
@@ -4211,10 +4211,10 @@
;; Unpredicated integer binary logical operations.
(define_insn "<optab><mode>3"
- [(set (match_operand:SVE_FULL_I 0 "register_operand" "=w, ?w, w")
- (LOGICAL:SVE_FULL_I
- (match_operand:SVE_FULL_I 1 "register_operand" "%0, w, w")
- (match_operand:SVE_FULL_I 2 "aarch64_sve_logical_operand" "vsl, vsl, w")))]
+ [(set (match_operand:SVE_I 0 "register_operand" "=w, ?w, w")
+ (LOGICAL:SVE_I
+ (match_operand:SVE_I 1 "register_operand" "%0, w, w")
+ (match_operand:SVE_I 2 "aarch64_sve_logical_operand" "vsl, vsl, w")))]
"TARGET_SVE"
"@
<logical>\t%0.<Vetype>, %0.<Vetype>, #%C2
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/load_const_offset_2.c b/gcc/testsuite/gcc.target/aarch64/sve/load_const_offset_2.c
index e02a6b5abee..0aab81b8560 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/load_const_offset_2.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/load_const_offset_2.c
@@ -1,5 +1,5 @@
/* { dg-do assemble { target aarch64_asm_sve_ok } } */
-/* { dg-options "-O2 -ftree-vectorize -save-temps" } */
+/* { dg-options "-O2 -ftree-vectorize -save-temps --param aarch64-sve-compare-costs=0" } */
#include <stdint.h>
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_1.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_1.c
new file mode 100644
index 00000000000..784035528f7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_1.c
@@ -0,0 +1,16 @@
+/* { dg-options "-O3 -msve-vector-bits=256" } */
+
+#include <stdint.h>
+
+void
+f (uint32_t *restrict dst, uint16_t *restrict src1, uint8_t *restrict src2)
+{
+ for (int i = 0; i < 7; ++i)
+ dst[i] = (uint16_t) (src1[i] & src2[i]);
+}
+
+/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s,} 1 } } */
+/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.s,} 1 } } */
+/* { dg-final { scan-assembler-times {\tand\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 1 } } */
+/* { dg-final { scan-assembler-times {\tuxth\tz[0-9]+\.s,} 1 } } */
+/* { dg-final { scan-assembler-times {\tst1w\tz[0-9]+\.s,} 1 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_2.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_2.c
new file mode 100644
index 00000000000..08b274512e1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_2.c
@@ -0,0 +1,17 @@
+/* { dg-options "-O3 -msve-vector-bits=256" } */
+
+#include <stdint.h>
+
+void
+f (uint64_t *restrict dst, uint16_t *restrict src1, uint8_t *restrict src2)
+{
+ for (int i = 0; i < 7; ++i)
+ dst[i] = (uint16_t) (src1[i] & src2[i]);
+}
+
+/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d,} 2 } } */
+/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.d,} 2 } } */
+/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.h,} 1 } } */
+/* { dg-final { scan-assembler-times {\tand\tz[0-9]+\.d,} 2 } } */
+/* { dg-final { scan-assembler-times {\tuxth\tz[0-9]+\.d,} 2 } } */
+/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_3.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_3.c
new file mode 100644
index 00000000000..c823470ca92
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_3.c
@@ -0,0 +1,17 @@
+/* { dg-options "-O3 -msve-vector-bits=256" } */
+
+#include <stdint.h>
+
+void
+f (uint64_t *restrict dst, uint32_t *restrict src1, uint8_t *restrict src2)
+{
+ for (int i = 0; i < 7; ++i)
+ dst[i] = (uint32_t) (src1[i] & src2[i]);
+}
+
+/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d,} 2 } } */
+/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.d,} 2 } } */
+/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.s,} 1 } } */
+/* { dg-final { scan-assembler-times {\tand\tz[0-9]+\.d,} 2 } } */
+/* { dg-final { scan-assembler-times {\tuxtw\tz[0-9]+\.d,} 2 } } */
+/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_4.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_4.c
new file mode 100644
index 00000000000..52c92911d9b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_4.c
@@ -0,0 +1,17 @@
+/* { dg-options "-O3 -msve-vector-bits=256" } */
+
+#include <stdint.h>
+
+void
+f (uint64_t *restrict dst, uint32_t *restrict src1, uint16_t *restrict src2)
+{
+ for (int i = 0; i < 7; ++i)
+ dst[i] = (uint32_t) (src1[i] & src2[i]);
+}
+
+/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d,} 2 } } */
+/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d,} 2 } } */
+/* { dg-final { scan-assembler-times {\tuxth\tz[0-9]+\.s,} 1 } } */
+/* { dg-final { scan-assembler-times {\tand\tz[0-9]+\.d,} 2 } } */
+/* { dg-final { scan-assembler-times {\tuxtw\tz[0-9]+\.d,} 2 } } */
+/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_5.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_5.c
new file mode 100644
index 00000000000..784035528f7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_5.c
@@ -0,0 +1,16 @@
+/* { dg-options "-O3 -msve-vector-bits=256" } */
+
+#include <stdint.h>
+
+void
+f (uint32_t *restrict dst, uint16_t *restrict src1, uint8_t *restrict src2)
+{
+ for (int i = 0; i < 7; ++i)
+ dst[i] = (uint16_t) (src1[i] & src2[i]);
+}
+
+/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s,} 1 } } */
+/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.s,} 1 } } */
+/* { dg-final { scan-assembler-times {\tand\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 1 } } */
+/* { dg-final { scan-assembler-times {\tuxth\tz[0-9]+\.s,} 1 } } */
+/* { dg-final { scan-assembler-times {\tst1w\tz[0-9]+\.s,} 1 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_6.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_6.c
new file mode 100644
index 00000000000..1552ed85302
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_6.c
@@ -0,0 +1,17 @@
+/* { dg-options "-O3 -msve-vector-bits=256" } */
+
+#include <stdint.h>
+
+void
+f (uint64_t *restrict dst, uint16_t *restrict src1, uint8_t *restrict src2)
+{
+ for (int i = 0; i < 7; ++i)
+ dst[i] = (uint16_t) (src1[i] & src2[i]);
+}
+
+/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d,} 2 } } */
+/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.d,} 2 } } */
+/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.h,} 1 } } */
+/* { dg-final { scan-assembler-times {\tand\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tuxth\tz[0-9]+\.d,} 2 } } */
+/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_7.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_7.c
new file mode 100644
index 00000000000..484d9daf38f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_7.c
@@ -0,0 +1,16 @@
+/* { dg-options "-O3 -msve-vector-bits=256" } */
+
+#include <stdint.h>
+
+void
+f (uint64_t *restrict dst, uint32_t *restrict src1, uint8_t *restrict src2){
+ for (int i = 0; i < 7; ++i)
+ dst[i] = (uint32_t) (src1[i] & src2[i]);
+}
+
+/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d,} 2 } } */
+/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.d,} 2 } } */
+/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.s,} 1 } } */
+/* { dg-final { scan-assembler-times {\tand\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tuxtw\tz[0-9]+\.d,} 2 } } */
+/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_1.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_1.c
new file mode 100644
index 00000000000..36a0b8c0c02
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_1.c
@@ -0,0 +1,16 @@
+/* { dg-options "-O3 -msve-vector-bits=256" } */
+
+#include <stdint.h>
+
+void
+f (uint32_t *restrict dst, uint16_t *restrict src1, uint8_t *restrict src2)
+{
+ for (int i = 0; i < 7; ++i)
+ dst[i] = (uint16_t) (src1[i] ^ src2[i]);
+}
+
+/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s,} 1 } } */
+/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.s,} 1 } } */
+/* { dg-final { scan-assembler-times {\teor\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 1 } } */
+/* { dg-final { scan-assembler-times {\tuxth\tz[0-9]+\.s,} 1 } } */
+/* { dg-final { scan-assembler-times {\tst1w\tz[0-9]+\.s,} 1 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_2.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_2.c
new file mode 100644
index 00000000000..23ddeb9f9b1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_2.c
@@ -0,0 +1,17 @@
+/* { dg-options "-O3 -msve-vector-bits=256" } */
+
+#include <stdint.h>
+
+void
+f (uint64_t *restrict dst, uint16_t *restrict src1, uint8_t *restrict src2)
+{
+ for (int i = 0; i < 7; ++i)
+ dst[i] = (uint16_t) (src1[i] ^ src2[i]);
+}
+
+/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d,} 2 } } */
+/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.d,} 2 } } */
+/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.h,} 1 } } */
+/* { dg-final { scan-assembler-times {\teor\tz[0-9]+\.d,} 2 } } */
+/* { dg-final { scan-assembler-times {\tuxth\tz[0-9]+\.d,} 2 } } */
+/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_3.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_3.c
new file mode 100644
index 00000000000..4dd1e085646
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_3.c
@@ -0,0 +1,17 @@
+/* { dg-options "-O3 -msve-vector-bits=256" } */
+
+#include <stdint.h>
+
+void
+f (uint64_t *restrict dst, uint32_t *restrict src1, uint8_t *restrict src2)
+{
+ for (int i = 0; i < 7; ++i)
+ dst[i] = (uint32_t) (src1[i] ^ src2[i]);
+}
+
+/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d,} 2 } } */
+/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.d,} 2 } } */
+/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.s,} 1 } } */
+/* { dg-final { scan-assembler-times {\teor\tz[0-9]+\.d,} 2 } } */
+/* { dg-final { scan-assembler-times {\tuxtw\tz[0-9]+\.d,} 2 } } */
+/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_4.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_4.c
new file mode 100644
index 00000000000..a31a2d425fa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_4.c
@@ -0,0 +1,17 @@
+/* { dg-options "-O3 -msve-vector-bits=256" } */
+
+#include <stdint.h>
+
+void
+f (uint64_t *restrict dst, uint32_t *restrict src1, uint16_t *restrict src2)
+{
+ for (int i = 0; i < 7; ++i)
+ dst[i] = (uint32_t) (src1[i] ^ src2[i]);
+}
+
+/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d,} 2 } } */
+/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d,} 2 } } */
+/* { dg-final { scan-assembler-times {\tuxth\tz[0-9]+\.s,} 1 } } */
+/* { dg-final { scan-assembler-times {\teor\tz[0-9]+\.d,} 2 } } */
+/* { dg-final { scan-assembler-times {\tuxtw\tz[0-9]+\.d,} 2 } } */
+/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_5.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_5.c
new file mode 100644
index 00000000000..36a0b8c0c02
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_5.c
@@ -0,0 +1,16 @@
+/* { dg-options "-O3 -msve-vector-bits=256" } */
+
+#include <stdint.h>
+
+void
+f (uint32_t *restrict dst, uint16_t *restrict src1, uint8_t *restrict src2)
+{
+ for (int i = 0; i < 7; ++i)
+ dst[i] = (uint16_t) (src1[i] ^ src2[i]);
+}
+
+/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s,} 1 } } */
+/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.s,} 1 } } */
+/* { dg-final { scan-assembler-times {\teor\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 1 } } */
+/* { dg-final { scan-assembler-times {\tuxth\tz[0-9]+\.s,} 1 } } */
+/* { dg-final { scan-assembler-times {\tst1w\tz[0-9]+\.s,} 1 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_6.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_6.c
new file mode 100644
index 00000000000..416567b21f7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_6.c
@@ -0,0 +1,17 @@
+/* { dg-options "-O3 -msve-vector-bits=256" } */
+
+#include <stdint.h>
+
+void
+f (uint64_t *restrict dst, uint16_t *restrict src1, uint8_t *restrict src2)
+{
+ for (int i = 0; i < 7; ++i)
+ dst[i] = (uint16_t) (src1[i] ^ src2[i]);
+}
+
+/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d,} 2 } } */
+/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.d,} 2 } } */
+/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.h,} 1 } } */
+/* { dg-final { scan-assembler-times {\teor\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tuxth\tz[0-9]+\.d,} 2 } } */
+/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_7.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_7.c
new file mode 100644
index 00000000000..3f7c3ddbba8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_7.c
@@ -0,0 +1,16 @@
+/* { dg-options "-O3 -msve-vector-bits=256" } */
+
+#include <stdint.h>
+
+void
+f (uint64_t *restrict dst, uint32_t *restrict src1, uint8_t *restrict src2){
+ for (int i = 0; i < 7; ++i)
+ dst[i] = (uint32_t) (src1[i] ^ src2[i]);
+}
+
+/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d,} 2 } } */
+/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.d,} 2 } } */
+/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.s,} 1 } } */
+/* { dg-final { scan-assembler-times {\teor\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tuxtw\tz[0-9]+\.d,} 2 } } */
+/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_1.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_1.c
new file mode 100644
index 00000000000..6131792c82f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_1.c
@@ -0,0 +1,16 @@
+/* { dg-options "-O3 -msve-vector-bits=256" } */
+
+#include <stdint.h>
+
+void
+f (uint32_t *restrict dst, uint16_t *restrict src1, uint8_t *restrict src2)
+{
+ for (int i = 0; i < 7; ++i)
+ dst[i] = (uint16_t) (src1[i] | src2[i]);
+}
+
+/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s,} 1 } } */
+/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.s,} 1 } } */
+/* { dg-final { scan-assembler-times {\torr\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 1 } } */
+/* { dg-final { scan-assembler-times {\tuxth\tz[0-9]+\.s,} 1 } } */
+/* { dg-final { scan-assembler-times {\tst1w\tz[0-9]+\.s,} 1 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_2.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_2.c
new file mode 100644
index 00000000000..593de65a02c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_2.c
@@ -0,0 +1,17 @@
+/* { dg-options "-O3 -msve-vector-bits=256" } */
+
+#include <stdint.h>
+
+void
+f (uint64_t *restrict dst, uint16_t *restrict src1, uint8_t *restrict src2)
+{
+ for (int i = 0; i < 7; ++i)
+ dst[i] = (uint16_t) (src1[i] | src2[i]);
+}
+
+/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d,} 2 } } */
+/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.d,} 2 } } */
+/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.h,} 1 } } */
+/* { dg-final { scan-assembler-times {\torr\tz[0-9]+\.d,} 2 } } */
+/* { dg-final { scan-assembler-times {\tuxth\tz[0-9]+\.d,} 2 } } */
+/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_3.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_3.c
new file mode 100644
index 00000000000..ec34e753eab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_3.c
@@ -0,0 +1,17 @@
+/* { dg-options "-O3 -msve-vector-bits=256" } */
+
+#include <stdint.h>
+
+void
+f (uint64_t *restrict dst, uint32_t *restrict src1, uint8_t *restrict src2)
+{
+ for (int i = 0; i < 7; ++i)
+ dst[i] = (uint32_t) (src1[i] | src2[i]);
+}
+
+/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d,} 2 } } */
+/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.d,} 2 } } */
+/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.s,} 1 } } */
+/* { dg-final { scan-assembler-times {\torr\tz[0-9]+\.d,} 2 } } */
+/* { dg-final { scan-assembler-times {\tuxtw\tz[0-9]+\.d,} 2 } } */
+/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_4.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_4.c
new file mode 100644
index 00000000000..561a104a23f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_4.c
@@ -0,0 +1,17 @@
+/* { dg-options "-O3 -msve-vector-bits=256" } */
+
+#include <stdint.h>
+
+void
+f (uint64_t *restrict dst, uint32_t *restrict src1, uint16_t *restrict src2)
+{
+ for (int i = 0; i < 7; ++i)
+ dst[i] = (uint32_t) (src1[i] | src2[i]);
+}
+
+/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d,} 2 } } */
+/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d,} 2 } } */
+/* { dg-final { scan-assembler-times {\tuxth\tz[0-9]+\.s,} 1 } } */
+/* { dg-final { scan-assembler-times {\torr\tz[0-9]+\.d,} 2 } } */
+/* { dg-final { scan-assembler-times {\tuxtw\tz[0-9]+\.d,} 2 } } */
+/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_5.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_5.c
new file mode 100644
index 00000000000..6131792c82f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_5.c
@@ -0,0 +1,16 @@
+/* { dg-options "-O3 -msve-vector-bits=256" } */
+
+#include <stdint.h>
+
+void
+f (uint32_t *restrict dst, uint16_t *restrict src1, uint8_t *restrict src2)
+{
+ for (int i = 0; i < 7; ++i)
+ dst[i] = (uint16_t) (src1[i] | src2[i]);
+}
+
+/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s,} 1 } } */
+/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.s,} 1 } } */
+/* { dg-final { scan-assembler-times {\torr\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 1 } } */
+/* { dg-final { scan-assembler-times {\tuxth\tz[0-9]+\.s,} 1 } } */
+/* { dg-final { scan-assembler-times {\tst1w\tz[0-9]+\.s,} 1 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_6.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_6.c
new file mode 100644
index 00000000000..3ce1c3fb1e6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_6.c
@@ -0,0 +1,17 @@
+/* { dg-options "-O3 -msve-vector-bits=256" } */
+
+#include <stdint.h>
+
+void
+f (uint64_t *restrict dst, uint16_t *restrict src1, uint8_t *restrict src2)
+{
+ for (int i = 0; i < 7; ++i)
+ dst[i] = (uint16_t) (src1[i] | src2[i]);
+}
+
+/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d,} 2 } } */
+/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.d,} 2 } } */
+/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.h,} 1 } } */
+/* { dg-final { scan-assembler-times {\torr\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tuxth\tz[0-9]+\.d,} 2 } } */
+/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_7.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_7.c
new file mode 100644
index 00000000000..e6a429167ea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_7.c
@@ -0,0 +1,16 @@
+/* { dg-options "-O3 -msve-vector-bits=256" } */
+
+#include <stdint.h>
+
+void
+f (uint64_t *restrict dst, uint32_t *restrict src1, uint8_t *restrict src2){
+ for (int i = 0; i < 7; ++i)
+ dst[i] = (uint32_t) (src1[i] | src2[i]);
+}
+
+/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d,} 2 } } */
+/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.d,} 2 } } */
+/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.s,} 1 } } */
+/* { dg-final { scan-assembler-times {\torr\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tuxtw\tz[0-9]+\.d,} 2 } } */
+/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/scatter_store_6.c b/gcc/testsuite/gcc.target/aarch64/sve/scatter_store_6.c
index ee31562440f..a9c37c4414b 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/scatter_store_6.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/scatter_store_6.c
@@ -1,5 +1,5 @@
/* { dg-do assemble { target aarch64_asm_sve_ok } } */
-/* { dg-options "-O2 -ftree-vectorize -fwrapv --save-temps" } */
+/* { dg-options "-O2 -ftree-vectorize -fwrapv --save-temps --param aarch64-sve-compare-costs=0" } */
#include <stdint.h>
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/scatter_store_7.c b/gcc/testsuite/gcc.target/aarch64/sve/scatter_store_7.c
index 784921e5d3c..147eadc63a4 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/scatter_store_7.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/scatter_store_7.c
@@ -1,5 +1,5 @@
/* { dg-do assemble { target aarch64_asm_sve_ok } } */
-/* { dg-options "-O2 -ftree-vectorize --save-temps" } */
+/* { dg-options "-O2 -ftree-vectorize --save-temps --param aarch64-sve-compare-costs=0" } */
#define INDEX16 uint16_t
#define INDEX32 uint32_t
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/strided_load_3.c b/gcc/testsuite/gcc.target/aarch64/sve/strided_load_3.c
index 8f720dcc1b6..2e7cd98e906 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/strided_load_3.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/strided_load_3.c
@@ -1,5 +1,5 @@
/* { dg-do assemble { target aarch64_asm_sve_ok } } */
-/* { dg-options "-O2 -ftree-vectorize --save-temps" } */
+/* { dg-options "-O2 -ftree-vectorize --save-temps --param aarch64-sve-compare-costs=0" } */
#include <stdint.h>
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/strided_store_3.c b/gcc/testsuite/gcc.target/aarch64/sve/strided_store_3.c
index 68835af5fe8..335f99bb5a9 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/strided_store_3.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/strided_store_3.c
@@ -1,5 +1,5 @@
/* { dg-do assemble { target aarch64_asm_sve_ok } } */
-/* { dg-options "-O2 -ftree-vectorize --save-temps" } */
+/* { dg-options "-O2 -ftree-vectorize --save-temps --param aarch64-sve-compare-costs=0" } */
#include <stdint.h>
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpack_signed_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpack_signed_1.c
index d4da3690f48..ecb6e99400c 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/unpack_signed_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/unpack_signed_1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -ftree-vectorize -fno-inline" } */
+/* { dg-options "-O2 -ftree-vectorize -fno-inline --param aarch64-sve-compare-costs=0" } */
#include <stdint.h>
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2020-08-22 21:42 [gcc/devel/autopar_devel] aarch64: add support for unpacked EOR, ORR and AND Giuliano Belinassi
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