From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2100) id 25C8F3840C1E; Sat, 22 Aug 2020 21:45:14 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 25C8F3840C1E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1598132714; bh=v2J7tgKLl25ndLC5c5SMnrhxd3Gy0Ad6lLz7pPjFEM8=; h=From:To:Subject:Date:From; b=mnhJQQDO0HO0qfps+WTjoQfh+ZwUZf6k7DDg8LaOzY0ucGCpkkyiBGIgjjksKzRH+ BE7VnqTazRQ7m8Fn7x58ZzQGm9z5mV4upj//oOx0ct0elw3v5LLxDoOQa6eNz+Opu3 Ea9YBhZIaQdlI1EOr/tOU2FR2kPEOAbHu6AHtkrs= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Giuliano Belinassi To: gcc-cvs@gcc.gnu.org Subject: [gcc/devel/autopar_devel] RISC-V: Optimize si to di zero-extend followed by left shift. X-Act-Checkin: gcc X-Git-Author: Jim Wilson X-Git-Refname: refs/heads/devel/autopar_devel X-Git-Oldrev: d7d9a0ccfb13ae84d8225acf70ef20af0b32f1e7 X-Git-Newrev: 34bbabf3864026754af82abe816c79f495e187f6 Message-Id: <20200822214514.25C8F3840C1E@sourceware.org> Date: Sat, 22 Aug 2020 21:45:14 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 22 Aug 2020 21:45:14 -0000 https://gcc.gnu.org/g:34bbabf3864026754af82abe816c79f495e187f6 commit 34bbabf3864026754af82abe816c79f495e187f6 Author: Jim Wilson Date: Sat May 30 17:04:17 2020 -0700 RISC-V: Optimize si to di zero-extend followed by left shift. This is potentially a sequence of 3 shifts, we which optimize to a sequence of 2 shifts. This can happen when unsigned int is used for array indexing. gcc/ * config/riscv/riscv.md (zero_extendsidi2_shifted): New. gcc/testsuite/ * gcc.target/riscv/zero-extend-5.c: New. Diff: --- gcc/config/riscv/riscv.md | 22 ++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/zero-extend-5.c | 8 ++++++++ 2 files changed, 30 insertions(+) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 434e064e095..f4bdb7d8cfe 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -1808,6 +1808,28 @@ operands[2] = GEN_INT (ctz_hwi (INTVAL (operands[2]))); }) +;; Handle SImode to DImode zero-extend combined with a left shift. This can +;; occur when unsigned int is used for array indexing. Split this into two +;; shifts. Otherwise we can get 3 shifts. + +(define_insn_and_split "zero_extendsidi2_shifted" + [(set (match_operand:DI 0 "register_operand" "=r") + (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r") + (match_operand:QI 2 "immediate_operand" "I")) + (match_operand 3 "immediate_operand" ""))) + (clobber (match_scratch:DI 4 "=&r"))] + "TARGET_64BIT + && ((INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff)" + "#" + "&& reload_completed" + [(set (match_dup 4) + (ashift:DI (match_dup 1) (const_int 32))) + (set (match_dup 0) + (lshiftrt:DI (match_dup 4) (match_dup 5)))] + "operands[5] = GEN_INT (32 - (INTVAL (operands [2])));" + [(set_attr "type" "shift") + (set_attr "mode" "DI")]) + ;; ;; .................... ;; diff --git a/gcc/testsuite/gcc.target/riscv/zero-extend-5.c b/gcc/testsuite/gcc.target/riscv/zero-extend-5.c new file mode 100644 index 00000000000..1a135b8c097 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zero-extend-5.c @@ -0,0 +1,8 @@ +/* { dg-do compile { target { riscv64*-*-* } } } */ +/* { dg-options "-march=rv64gc -mabi=lp64 -O2" } */ +int +sub (unsigned int i, unsigned int j, unsigned int k, int *array) +{ + return array[i] + array[j] + array[k]; +} +/* { dg-final { scan-assembler-times "slli" 3 } } */