public inbox for gcc-cvs@sourceware.org
help / color / mirror / Atom feed
* [gcc/devel/autopar_devel] aarch64: Fix an ICE in aarch64_short_vector_p [PR95459]
@ 2020-08-22 21:52 Giuliano Belinassi
0 siblings, 0 replies; only message in thread
From: Giuliano Belinassi @ 2020-08-22 21:52 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:91237fa78893ec7764bbf0d850c41b5c7f43f9e7
commit 91237fa78893ec7764bbf0d850c41b5c7f43f9e7
Author: Fei Yang <felix.yang@huawei.com>
Date: Tue Jun 2 18:17:34 2020 +0100
aarch64: Fix an ICE in aarch64_short_vector_p [PR95459]
In aarch64_short_vector_p, we are simply checking whether a type (and a mode)
is a 64/128-bit short vector or not. This should not be affected by the value
of TARGET_SVE. Simply leave later code to report an error if SVE is disabled.
2020-06-02 Felix Yang <felix.yang@huawei.com>
gcc/
PR target/95459
* config/aarch64/aarch64.c (aarch64_short_vector_p):
Leave later code to report an error if SVE is disabled.
gcc/testsuite/
PR target/95459
* gcc.target/aarch64/mgeneral-regs_6.c: New test.
Diff:
---
gcc/config/aarch64/aarch64.c | 3 ++-
gcc/testsuite/gcc.target/aarch64/mgeneral-regs_6.c | 15 +++++++++++++++
2 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 7feff77adf6..6352d4ff78a 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -16800,7 +16800,8 @@ aarch64_short_vector_p (const_tree type,
{
/* Rely only on the type, not the mode, when processing SVE types. */
if (type && aarch64_some_values_include_pst_objects_p (type))
- gcc_assert (aarch64_sve_mode_p (mode));
+ /* Leave later code to report an error if SVE is disabled. */
+ gcc_assert (!TARGET_SVE || aarch64_sve_mode_p (mode));
else
size = GET_MODE_SIZE (mode);
}
diff --git a/gcc/testsuite/gcc.target/aarch64/mgeneral-regs_6.c b/gcc/testsuite/gcc.target/aarch64/mgeneral-regs_6.c
new file mode 100644
index 00000000000..427ae6a0e4b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/mgeneral-regs_6.c
@@ -0,0 +1,15 @@
+/* { dg-options "-O2 -march=armv8.2-a+sve" } */
+/* { dg-prune-output "compilation terminated" } */
+
+#include <arm_sve.h>
+
+#pragma GCC push_options
+#pragma GCC target "general-regs-only"
+
+svint8x2_t
+foo (svint8_t x0, svint8_t x1) /* { dg-error {'foo' requires the SVE ISA extension} } */
+{
+ return svcreate2 (x0, x1); /* { dg-error {ACLE function 'svcreate2_s8' is incompatible with the use of '-mgeneral-regs-only'} } */
+}
+
+#pragma GCC pop_options
^ permalink raw reply [flat|nested] only message in thread
only message in thread, other threads:[~2020-08-22 21:52 UTC | newest]
Thread overview: (only message) (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-08-22 21:52 [gcc/devel/autopar_devel] aarch64: Fix an ICE in aarch64_short_vector_p [PR95459] Giuliano Belinassi
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).