From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2100) id 03B023875449; Sat, 22 Aug 2020 21:52:42 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 03B023875449 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1598133162; bh=OxnAeMOKNoSsaA9FWOU7Dr2SBAlM6mYPiVN0Quqngd8=; h=From:To:Subject:Date:From; b=ySKP+c0NoB1PINFJiRoSujwsP8T+7iF3/qsKVcmVwDk9qQg0Zvj+4aUADt/hJSKak 8wJl2bS9i0qtJqrYQJijG8NFsm7LwjQNtPwdx0ldtXYLwmRiCFnMEOEOcazHki0UjN 6BHCf0EgXDAL3N+YZgSZFwz1e8IE6z/J6Mzsd6/I= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Giuliano Belinassi To: gcc-cvs@gcc.gnu.org Subject: [gcc/devel/autopar_devel] aarch64: Fix an ICE in aarch64_short_vector_p [PR95459] X-Act-Checkin: gcc X-Git-Author: Fei Yang X-Git-Refname: refs/heads/devel/autopar_devel X-Git-Oldrev: a4825ab38d942656c960e4f09efd1deae8bcedb5 X-Git-Newrev: 91237fa78893ec7764bbf0d850c41b5c7f43f9e7 Message-Id: <20200822215242.03B023875449@sourceware.org> Date: Sat, 22 Aug 2020 21:52:42 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 22 Aug 2020 21:52:42 -0000 https://gcc.gnu.org/g:91237fa78893ec7764bbf0d850c41b5c7f43f9e7 commit 91237fa78893ec7764bbf0d850c41b5c7f43f9e7 Author: Fei Yang Date: Tue Jun 2 18:17:34 2020 +0100 aarch64: Fix an ICE in aarch64_short_vector_p [PR95459] In aarch64_short_vector_p, we are simply checking whether a type (and a mode) is a 64/128-bit short vector or not. This should not be affected by the value of TARGET_SVE. Simply leave later code to report an error if SVE is disabled. 2020-06-02 Felix Yang gcc/ PR target/95459 * config/aarch64/aarch64.c (aarch64_short_vector_p): Leave later code to report an error if SVE is disabled. gcc/testsuite/ PR target/95459 * gcc.target/aarch64/mgeneral-regs_6.c: New test. Diff: --- gcc/config/aarch64/aarch64.c | 3 ++- gcc/testsuite/gcc.target/aarch64/mgeneral-regs_6.c | 15 +++++++++++++++ 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 7feff77adf6..6352d4ff78a 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -16800,7 +16800,8 @@ aarch64_short_vector_p (const_tree type, { /* Rely only on the type, not the mode, when processing SVE types. */ if (type && aarch64_some_values_include_pst_objects_p (type)) - gcc_assert (aarch64_sve_mode_p (mode)); + /* Leave later code to report an error if SVE is disabled. */ + gcc_assert (!TARGET_SVE || aarch64_sve_mode_p (mode)); else size = GET_MODE_SIZE (mode); } diff --git a/gcc/testsuite/gcc.target/aarch64/mgeneral-regs_6.c b/gcc/testsuite/gcc.target/aarch64/mgeneral-regs_6.c new file mode 100644 index 00000000000..427ae6a0e4b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/mgeneral-regs_6.c @@ -0,0 +1,15 @@ +/* { dg-options "-O2 -march=armv8.2-a+sve" } */ +/* { dg-prune-output "compilation terminated" } */ + +#include + +#pragma GCC push_options +#pragma GCC target "general-regs-only" + +svint8x2_t +foo (svint8_t x0, svint8_t x1) /* { dg-error {'foo' requires the SVE ISA extension} } */ +{ + return svcreate2 (x0, x1); /* { dg-error {ACLE function 'svcreate2_s8' is incompatible with the use of '-mgeneral-regs-only'} } */ +} + +#pragma GCC pop_options