[gcc/devel/c++-modules] Using gen_int_mode instead of GEN_INT to avoid ICE caused by type promotion.

[gcc/devel/c++-modules] Using gen_int_mode instead of GEN_INT to avoid ICE caused by type promotion.

[Nathan Sidwell]

https://gcc.gnu.org/g:c44c2a3b0559979e3694ee2ab6860ec95fa3068a

commit c44c2a3b0559979e3694ee2ab6860ec95fa3068a
Author: liuhongt <hongtao.liu@intel.com>
Date:   Wed Jul 22 14:37:24 2020 +0800

    Using gen_int_mode instead of GEN_INT to avoid ICE caused by type promotion.
    
    2020-07-22  Hongtao Liu  <hongtao.liu@intel.com>
    
    gcc/
            PR target/96262
            * config/i386/i386-expand.c
            (ix86_expand_vec_shift_qihi_constant): Refine.
    
    gcc/testsuite/
            * gcc.target/i386/pr96262-1.c: New test.

Diff:
---
 gcc/config/i386/i386-expand.c             |  6 +++---
 gcc/testsuite/gcc.target/i386/pr96262-1.c | 11 +++++++++++
 2 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c
index 61618636cff..a284f7e5bb4 100644
--- a/gcc/config/i386/i386-expand.c
+++ b/gcc/config/i386/i386-expand.c
@@ -19604,7 +19604,7 @@ bool
 ix86_expand_vec_shift_qihi_constant (enum rtx_code code, rtx dest, rtx op1, rtx op2)
 {
   machine_mode qimode, himode;
-  unsigned int and_constant, xor_constant;
+  HOST_WIDE_INT and_constant, xor_constant;
   HOST_WIDE_INT shift_amount;
   rtx vec_const_and, vec_const_xor;
   rtx tmp, op1_subreg;
@@ -19679,7 +19679,7 @@ ix86_expand_vec_shift_qihi_constant (enum rtx_code code, rtx dest, rtx op1, rtx
   emit_move_insn (dest, simplify_gen_subreg (qimode, tmp, himode, 0));
   emit_move_insn (vec_const_and,
 		  ix86_build_const_vector (qimode, true,
-					   GEN_INT (and_constant)));
+					   gen_int_mode (and_constant, QImode)));
   emit_insn (gen_and (dest, dest, vec_const_and));
 
   /* For ASHIFTRT, perform extra operation like
@@ -19690,7 +19690,7 @@ ix86_expand_vec_shift_qihi_constant (enum rtx_code code, rtx dest, rtx op1, rtx
       vec_const_xor = gen_reg_rtx (qimode);
       emit_move_insn (vec_const_xor,
 		      ix86_build_const_vector (qimode, true,
-					       GEN_INT (xor_constant)));
+					       gen_int_mode (xor_constant, QImode)));
       emit_insn (gen_xor (dest, dest, vec_const_xor));
       emit_insn (gen_sub (dest, dest, vec_const_xor));
     }
diff --git a/gcc/testsuite/gcc.target/i386/pr96262-1.c b/gcc/testsuite/gcc.target/i386/pr96262-1.c
new file mode 100644
index 00000000000..1825388072e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr96262-1.c
@@ -0,0 +1,11 @@
+/* PR target/96262 */
+/* { dg-do compile } */
+/* { dg-options "-mavx512bw -O" } */
+
+typedef char __attribute__ ((__vector_size__ (64))) V;
+
+V
+foo (V v)
+{
+  return ~(v << 1);
+}