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* [gcc(refs/users/meissner/heads/work017)] Undo last patch.
@ 2020-09-15 14:25 Michael Meissner
0 siblings, 0 replies; 2+ messages in thread
From: Michael Meissner @ 2020-09-15 14:25 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:891821fb6542efc4a63dd1a78de343fb252a09f2
commit 891821fb6542efc4a63dd1a78de343fb252a09f2
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Sep 15 10:13:47 2020 -0400
Undo last patch.
gcc/
2020-09-15 Michael Meissner <meissner@linux.ibm.com>
Undo
* config/rs6000/rs6000.c (rs6000_emit_minmax): Add support for ISA
3.1 IEEE 128-bit floating point xsmaxcqp and xsmincqp instructions.
(s<minmax><mode>3): Add support for the ISA 3.1 IEEE 128-bit
minimum and maximum instructions.
gcc/testsuite/
2020-09-15 Michael Meissner <meissner@linux.ibm.com>
Undo
* gcc.target/powerpc/float128-minmax-2.c: New test.
Diff:
---
gcc/config/rs6000/rs6000.c | 3 +--
gcc/config/rs6000/rs6000.md | 11 -----------
gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c | 15 ---------------
3 files changed, 1 insertion(+), 28 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index b3a50cb6517..6d0c5509b0e 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -15462,8 +15462,7 @@ rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
/* VSX/altivec have direct min/max insns. */
if ((code == SMAX || code == SMIN)
&& (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)
- || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode))
- || (FLOAT128_IEEE_P (mode) && TARGET_POWER10)))
+ || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode))))
{
emit_insn (gen_rtx_SET (dest, gen_rtx_fmt_ee (code, mode, op0, op1)));
return;
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 96907ef5c6f..9c5a22823c0 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -5163,17 +5163,6 @@
}
[(set_attr "type" "fp")])
-;; Min/max for ISA 3.1 IEEE 128-bit floating point
-(define_insn "s<minmax><mode>3"
- [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
- (fp_minmax:IEEE128
- (match_operand:IEEE128 1 "altivec_register_operand" "v")
- (match_operand:IEEE128 2 "altivec_register_operand" "v")))]
- "TARGET_POWER10"
- "xs<minmax>cqp %0,%1,%2"
- [(set_attr "type" "vecfloat")
- (set_attr "size" "128")])
-
;; The conditional move instructions allow us to perform max and min operations
;; even when we don't have the appropriate max/min instruction using the FSEL
;; instruction.
diff --git a/gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c b/gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c
deleted file mode 100644
index c71ba08c9f8..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c
+++ /dev/null
@@ -1,15 +0,0 @@
-/* { dg-require-effective-target ppc_float128_hw } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -ffast-math" } */
-
-#ifndef TYPE
-#define TYPE _Float128
-#endif
-
-/* Test that the fminf128/fmaxf128 functions generate if/then/else and not a
- call. */
-TYPE f128_min (TYPE a, TYPE b) { return __builtin_fminf128 (a, b); }
-TYPE f128_max (TYPE a, TYPE b) { return __builtin_fmaxf128 (a, b); }
-
-/* { dg-final { scan-assembler {\mxsmaxcqp\M} } } */
-/* { dg-final { scan-assembler {\mxsmincqp\M} } } */
^ permalink raw reply [flat|nested] 2+ messages in thread
* [gcc(refs/users/meissner/heads/work017)] Undo last patch.
@ 2020-09-15 16:45 Michael Meissner
0 siblings, 0 replies; 2+ messages in thread
From: Michael Meissner @ 2020-09-15 16:45 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:3effc26de6a33a7994d714bafa36d35d5311a9c2
commit 3effc26de6a33a7994d714bafa36d35d5311a9c2
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Sep 15 12:44:45 2020 -0400
Undo last patch.
gcc/
2020-09-15 Michael Meissner <meissner@linux.ibm.com>
Undo
* config/rs6000/rs6000.c (init_float128_ieee): Use a different
name for IEEE 128-bit long double complex multiply and divide.
libgcc/
2020-09-15 Michael Meissner <meissner@linux.ibm.com>
Undo
* config/rs6000/_divkc3.c (__divkc3x): Provide alias with
alternate name.
* config/rs6000/_mulkc3.c (__mulkc3x): Provide alias with
alternate name.
* config/rs6000/float128-ifunc.c (Add alternate aliases __divkc3x
and __mulkc3x).
* config/rs6000/quad-float128.c (__divkc3x): New declaration.
(__mulkc3x): New declaration.
Diff:
---
gcc/config/rs6000/rs6000.c | 9 +++------
libgcc/config/rs6000/_divkc3.c | 8 --------
libgcc/config/rs6000/_mulkc3.c | 7 -------
libgcc/config/rs6000/float128-ifunc.c | 9 ---------
libgcc/config/rs6000/quad-float128.h | 6 +-----
5 files changed, 4 insertions(+), 35 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index ef7e5e9fd7f..1ba23ddb350 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -10370,10 +10370,7 @@ init_float128_ieee (machine_mode mode)
/* Set up to call __mulkc3 and __divkc3 under -mabi=ieeelongdouble. If
we have clone or target attributes, this will be called a second
- time. We want to create the built-in function only once.
-
- Unfortunately, we cannot call it __mulkc3 or __divkc3. Add an 'x'
- suffix, and in libgcc provide both names. */
+ time. We want to create the built-in function only once. */
if (mode == TFmode && TARGET_IEEEQUAD && !complex_muldiv_init_p)
{
complex_muldiv_init_p = true;
@@ -10391,8 +10388,8 @@ init_float128_ieee (machine_mode mode)
long_double_type_node,
NULL_TREE);
- create_complex_muldiv ("__mulkc3x", fncode_mul, fntype);
- create_complex_muldiv ("__divkc3x", fncode_div, fntype);
+ create_complex_muldiv ("__mulkc3", fncode_mul, fntype);
+ create_complex_muldiv ("__divkc3", fncode_div, fntype);
}
set_optab_libfunc (add_optab, mode, "__addkf3");
diff --git a/libgcc/config/rs6000/_divkc3.c b/libgcc/config/rs6000/_divkc3.c
index e8d2213bb73..91482afe4c4 100644
--- a/libgcc/config/rs6000/_divkc3.c
+++ b/libgcc/config/rs6000/_divkc3.c
@@ -91,11 +91,3 @@ __divkc3 (TFtype a, TFtype b, TFtype c, TFtype d)
__imag__ res = y;
return res;
}
-
-/* Provide an alternate name for __divkc3 that is used when when long double is
- IEEE 128. Only do this if we aren't creating ifunc's to handle software
- vs. hardware IEEE 128-bit functions. */
-#ifndef __divkc3
-TCtype __divkc3x (TFtype, TFtype, TFtype, TFtype)
- __attribute__ ((weak, alias ("__divkc3")));
-#endif
diff --git a/libgcc/config/rs6000/_mulkc3.c b/libgcc/config/rs6000/_mulkc3.c
index 408d54e8c8e..665e1451498 100644
--- a/libgcc/config/rs6000/_mulkc3.c
+++ b/libgcc/config/rs6000/_mulkc3.c
@@ -96,10 +96,3 @@ __mulkc3 (TFtype a, TFtype b, TFtype c, TFtype d)
return res;
}
-/* Provide an alternate name for __mulkc3 that is used when when long double is
- IEEE 128. Only do this if we aren't creating ifunc's to handle software
- vs. hardware IEEE 128-bit functions. */
-#ifndef __mulkc3
-TCtype __mulkc3x (TFtype, TFtype, TFtype, TFtype)
- __attribute__ ((weak, alias ("__mulkc3")));
-#endif
diff --git a/libgcc/config/rs6000/float128-ifunc.c b/libgcc/config/rs6000/float128-ifunc.c
index 1b8567aae1a..c2f65912a74 100644
--- a/libgcc/config/rs6000/float128-ifunc.c
+++ b/libgcc/config/rs6000/float128-ifunc.c
@@ -320,12 +320,3 @@ TCtype __mulkc3 (TFtype, TFtype, TFtype, TFtype)
TCtype __divkc3 (TFtype, TFtype, TFtype, TFtype)
__attribute__ ((__ifunc__ ("__divkc3_resolve")));
-
- /* We needed to use alternate names for complex multiple and divide for the
- case where long double is IEEE 128-bit. Resolve these to be the same as
- the normal function. */
-TCtype __mulkc3x (TFtype, TFtype, TFtype, TFtype)
- __attribute__ ((__ifunc__ ("__mulkc3_resolve")));
-
-TCtype __divkc3x (TFtype, TFtype, TFtype, TFtype)
- __attribute__ ((__ifunc__ ("__divkc3_resolve")));
diff --git a/libgcc/config/rs6000/quad-float128.h b/libgcc/config/rs6000/quad-float128.h
index 8e526f6b56b..32ef328a8ea 100644
--- a/libgcc/config/rs6000/quad-float128.h
+++ b/libgcc/config/rs6000/quad-float128.h
@@ -167,14 +167,10 @@ extern TFtype __floatundikf (UDItype_ppc);
extern IBM128_TYPE __extendkftf2 (TFtype);
extern TFtype __trunctfkf2 (IBM128_TYPE);
-/* Complex __float128 built on __float128 interfaces. The 'x' version is used
- when long double is IEEE 128 to avoid reusing the same name. */
+/* Complex __float128 built on __float128 interfaces. */
extern TCtype __mulkc3 (TFtype, TFtype, TFtype, TFtype);
extern TCtype __divkc3 (TFtype, TFtype, TFtype, TFtype);
-extern TCtype __mulkc3x (TFtype, TFtype, TFtype, TFtype);
-extern TCtype __divkc3x (TFtype, TFtype, TFtype, TFtype);
-
/* Implementation of conversions between __ibm128 and __float128, to allow the
same code to be used on systems with IEEE 128-bit emulation and with IEEE
128-bit hardware support. */
^ permalink raw reply [flat|nested] 2+ messages in thread
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