[gcc(refs/vendors/redhat/heads/gcc-8-branch)] rs6000: Fix infinite loop building ghostscript and icu [PR93658]

[gcc(refs/vendors/redhat/heads/gcc-8-branch)] rs6000: Fix infinite loop building ghostscript and icu [PR93658]

[Jakub Jelinek]

https://gcc.gnu.org/g:4a2bb49ddce8b339a16e34aa9a0fb9ef08b12f44

commit 4a2bb49ddce8b339a16e34aa9a0fb9ef08b12f44
Author: Peter Bergner <bergner@linux.ibm.com>
Date:   Sun Feb 23 22:04:44 2020 -0600

    rs6000: Fix infinite loop building ghostscript and icu [PR93658]
    
    Fix rs6000_legitimate_address_p(), which erroneously marks a valid Altivec
    address as being invalid, which causes LRA's process_address()  to go into
    an infinite loop spilling the same address over and over again.
    Include Mike's earlier commits that fix bugs this patch exposes.
    
            Backport from master
            2020-02-20  Peter Bergner  <bergner@linux.ibm.com>
    
            PR target/93658
            * config/rs6000/rs6000.c (rs6000_legitimate_address_p): Handle VSX
            vector modes.
    
            * gcc.target/powerpc/pr93658.c: New test.
            * gcc.target/powerpc/vsx-vector-6-le.c: Update fragile insn count.

Diff:
---
 gcc/ChangeLog                                      |  9 +++++++++
 gcc/config/rs6000/rs6000.c                         |  2 +-
 gcc/testsuite/ChangeLog                            |  9 +++++++++
 gcc/testsuite/gcc.target/powerpc/pr93658.c         | 20 ++++++++++++++++++++
 gcc/testsuite/gcc.target/powerpc/vsx-vector-6-le.c |  2 +-
 5 files changed, 40 insertions(+), 2 deletions(-)

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 90cffb5bb14..794b37961ad 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2020-02-23  Peter Bergner  <bergner@linux.ibm.com>
+
+	Backport from master
+	2020-02-20  Peter Bergner  <bergner@linux.ibm.com>
+
+	PR target/93658
+	* config/rs6000/rs6000.c (rs6000_legitimate_address_p): Handle VSX
+	vector modes.
+
 2020-02-23  Peter Bergner  <bergner@linux.ibm.com>
 
 	Backport from master
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index acfae128872..bb257e53918 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -9951,7 +9951,7 @@ rs6000_legitimate_address_p (machine_mode mode, rtx x, bool reg_ok_strict)
   bool quad_offset_p = mode_supports_vsx_dform_quad (mode);
 
   /* If this is an unaligned stvx/ldvx type address, discard the outer AND.  */
-  if (VECTOR_MEM_ALTIVEC_P (mode)
+  if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
       && GET_CODE (x) == AND
       && GET_CODE (XEXP (x, 1)) == CONST_INT
       && INTVAL (XEXP (x, 1)) == -16)
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 2c2bb804964..7d822b619fc 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,12 @@
+2020-02-23  Peter Bergner  <bergner@linux.ibm.com>
+
+	Backport from master
+	2020-02-20  Peter Bergner  <bergner@linux.ibm.com>
+
+	PR target/93658
+	* gcc.target/powerpc/pr93658.c: New test.
+	* gcc.target/powerpc/vsx-vector-6-le.c: Update fragile insn count.
+
 2020-02-20  H.J. Lu  <hongjiu.lu@intel.com>
 
 	Backport from master
diff --git a/gcc/testsuite/gcc.target/powerpc/pr93658.c b/gcc/testsuite/gcc.target/powerpc/pr93658.c
new file mode 100644
index 00000000000..0170d34d259
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr93658.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -fstack-protector-strong -mcpu=power8" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* PR93658: Failure compiling this test is an infinite loop in LRA's
+   process_address(), so set a short timeout limit.  */
+/* { dg-timeout 5 } */
+
+void bar();
+char b;
+void
+foo (void)
+{
+  char a;
+  int d = b;
+  char *e = &a;
+  while (d)
+    *e++ = --d;
+  bar ();
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-le.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-le.c
index fe7eeb12ff9..dc6ccb77d1f 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-le.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-le.c
@@ -14,7 +14,7 @@
    their usage counts being stable.  Therefore, we just ensure at least one
    xxlor instruction was generated.  */
 /* { dg-final { scan-assembler "xxlor" } } */
-/* { dg-final { scan-assembler-times "xvcmpeqdp" 5 } } */
+/* { dg-final { scan-assembler-times "xvcmpeqdp" 6 } } */
 /* { dg-final { scan-assembler-times "xvcmpgtdp" 8 } } */
 /* { dg-final { scan-assembler-times "xvcmpgedp" 6 } } */
 /* { dg-final { scan-assembler-times "xvrdpim" 1 } } */