[gcc(refs/vendors/redhat/heads/gcc-8-branch)] arm: correct constraints on movsi_compare0 [PR91913]

[gcc(refs/vendors/redhat/heads/gcc-8-branch)] arm: correct constraints on movsi_compare0 [PR91913]

[Jakub Jelinek]

https://gcc.gnu.org/g:d3ebe65d6808196f89362169a16517fe7550b7c3

commit d3ebe65d6808196f89362169a16517fe7550b7c3
Author: Richard Earnshaw <rearnsha@arm.com>
Date:   Fri Mar 6 10:04:51 2020 +0000

    arm: correct constraints on movsi_compare0 [PR91913]
    
    The peephole that detects a mov of one register to another followed by
    a comparison of the original register against zero is only used in Arm
    state; but the instruction that matches this is generic to all 32-bit
    compilation states.  That instruction lacks support for SP which is
    permitted in Arm state, but has restrictions in Thumb2 code.
    
    This patch fixes the problem by allowing SP when in ARM state for all
    registers; in Thumb state it allows SP only as a source when the
    register really is copied to another target.
    
    gcc/ChangeLog:
            PR target/91913
            Backport from master
            * config/arm/arm.md (movsi_compare0): Allow SP as a source register
            in Thumb state and also as a destination in Arm state.  Add T16
            variants.
    
    gcc/testsuite/ChangeLog:
            2020-02-10  Jakub Jelinek  <jakub@redhat.com>
    
            PR target/91913
            Backport from master
            * gfortran.dg/pr91913.f90: New test.

Diff:
---
 gcc/ChangeLog                         | 10 ++++++++++
 gcc/config/arm/arm.md                 | 11 ++++++++---
 gcc/testsuite/ChangeLog               |  8 ++++++++
 gcc/testsuite/gfortran.dg/pr91913.f90 |  5 +++++
 4 files changed, 31 insertions(+), 3 deletions(-)

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 75b14c5b3ad..c504374ee89 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,13 @@
+2020-03-12  Richard Earnshaw  <rearnsha@arm.com>
+
+	Backport from master
+	2020-02-10  Richard Earnshaw  <rearnsha@arm.com>
+
+	PR target/91913
+	* config/arm/arm.md (movsi_compare0): Allow SP as a source register
+	in Thumb state and also as a destination in Arm state.  Add T16
+	variants.
+
 2020-02-27  Jakub Jelinek  <jakub@redhat.com>
 
 	PR c/93949
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index f78e1477eab..6d6b37719e0 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -6312,16 +6312,21 @@
 
 (define_insn "*movsi_compare0"
   [(set (reg:CC CC_REGNUM)
-	(compare:CC (match_operand:SI 1 "s_register_operand" "0,r")
+	(compare:CC (match_operand:SI 1 "s_register_operand" "0,0,l,rk,rk")
 		    (const_int 0)))
-   (set (match_operand:SI 0 "s_register_operand" "=r,r")
+   (set (match_operand:SI 0 "s_register_operand" "=l,rk,l,r,rk")
 	(match_dup 1))]
   "TARGET_32BIT"
   "@
    cmp%?\\t%0, #0
+   cmp%?\\t%0, #0
+   subs%?\\t%0, %1, #0
+   subs%?\\t%0, %1, #0
    subs%?\\t%0, %1, #0"
   [(set_attr "conds" "set")
-   (set_attr "type" "alus_imm,alus_imm")]
+   (set_attr "arch" "t2,*,t2,t2,a")
+   (set_attr "type" "alus_imm")
+   (set_attr "length" "2,4,2,4,4")]
 )
 
 ;; Subroutine to store a half word from a register into memory.
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index be6fd5d321b..fd1eb8508a9 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2020-03-12  Richard Earnshaw  <rearnsha@arm.com>
+
+	Backport from master
+	2020-02-10  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/91913
+	* gfortran.dg/pr91913.f90: New test.
+
 2020-02-27  Jakub Jelinek  <jakub@redhat.com>
 
 	PR c/93949
diff --git a/gcc/testsuite/gfortran.dg/pr91913.f90 b/gcc/testsuite/gfortran.dg/pr91913.f90
new file mode 100644
index 00000000000..7d5477ac0c3
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/pr91913.f90
@@ -0,0 +1,5 @@
+! PR target/91913
+! { dg-do compile }
+! { dg-options "-std=legacy -Ofast --param max-cse-insns=0 -fno-schedule-insns -fsanitize=null" }
+
+include 'string_ctor_1.f90'