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* [gcc(refs/vendors/redhat/heads/gcc-8-branch)] aarch64: Improve swp generation
@ 2020-09-17 16:57 Jakub Jelinek
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From: Jakub Jelinek @ 2020-09-17 16:57 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:235a510be4f729bc4a31ca66a90207593764bd84
commit 235a510be4f729bc4a31ca66a90207593764bd84
Author: Andre Vieira <andre.simoesdiasvieira@arm.com>
Date: Thu Apr 16 10:16:09 2020 +0100
aarch64: Improve swp generation
Allow zero as an input; fix constraints; avoid unnecessary split.
2020-04-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
Backport from mainline.
2018-10-31 Richard Henderson <richard.henderson@linaro.org>
* config/aarch64/aarch64.c (aarch64_emit_atomic_swap): Remove.
(aarch64_gen_atomic_ldop): Don't call it.
* config/aarch64/atomics.md (atomic_exchange<ALLI>):
Use aarch64_reg_or_zero.
(aarch64_atomic_exchange<ALLI>): Likewise.
(aarch64_atomic_exchange<ALLI>_lse): Remove split; remove & from
operand 0; use aarch64_reg_or_zero for input; merge ...
(aarch64_atomic_swp<ALLI>): ... this and remove.
Diff:
---
gcc/ChangeLog | 14 +++++++++++++
gcc/config/aarch64/aarch64.c | 25 ----------------------
gcc/config/aarch64/atomics.md | 49 +++++++++++++------------------------------
3 files changed, 29 insertions(+), 59 deletions(-)
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 81c8a9bc505..37a87338593 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,17 @@
+2020-04-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ Backport from mainline.
+ 2018-10-31 Richard Henderson <richard.henderson@linaro.org>
+
+ * config/aarch64/aarch64.c (aarch64_emit_atomic_swap): Remove.
+ (aarch64_gen_atomic_ldop): Don't call it.
+ * config/aarch64/atomics.md (atomic_exchange<ALLI>):
+ Use aarch64_reg_or_zero.
+ (aarch64_atomic_exchange<ALLI>): Likewise.
+ (aarch64_atomic_exchange<ALLI>_lse): Remove split; remove & from
+ operand 0; use aarch64_reg_or_zero for input; merge ...
+ (aarch64_atomic_swp<ALLI>): ... this and remove.
+
2020-04-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
Backport from mainline.
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index b6a6e314153..bac69474598 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -14454,27 +14454,6 @@ aarch64_emit_bic (machine_mode mode, rtx dst, rtx s1, rtx s2, int shift)
emit_insn (gen (dst, s2, shift_rtx, s1));
}
-/* Emit an atomic swap. */
-
-static void
-aarch64_emit_atomic_swap (machine_mode mode, rtx dst, rtx value,
- rtx mem, rtx model)
-{
- rtx (*gen) (rtx, rtx, rtx, rtx);
-
- switch (mode)
- {
- case E_QImode: gen = gen_aarch64_atomic_swpqi; break;
- case E_HImode: gen = gen_aarch64_atomic_swphi; break;
- case E_SImode: gen = gen_aarch64_atomic_swpsi; break;
- case E_DImode: gen = gen_aarch64_atomic_swpdi; break;
- default:
- gcc_unreachable ();
- }
-
- emit_insn (gen (dst, mem, value, model));
-}
-
/* Operations supported by aarch64_emit_atomic_load_op. */
enum aarch64_atomic_load_op_code
@@ -14587,10 +14566,6 @@ aarch64_gen_atomic_ldop (enum rtx_code code, rtx out_data, rtx out_result,
a SET then emit a swap instruction and finish. */
switch (code)
{
- case SET:
- aarch64_emit_atomic_swap (mode, out_data, src, mem, model_rtx);
- return;
-
case MINUS:
/* Negate the value and treat it as a PLUS. */
{
diff --git a/gcc/config/aarch64/atomics.md b/gcc/config/aarch64/atomics.md
index b0e84b8addd..6cc14fbf6c1 100644
--- a/gcc/config/aarch64/atomics.md
+++ b/gcc/config/aarch64/atomics.md
@@ -136,7 +136,7 @@
(define_expand "atomic_exchange<mode>"
[(match_operand:ALLI 0 "register_operand" "")
(match_operand:ALLI 1 "aarch64_sync_memory_operand" "")
- (match_operand:ALLI 2 "register_operand" "")
+ (match_operand:ALLI 2 "aarch64_reg_or_zero" "")
(match_operand:SI 3 "const_int_operand" "")]
""
{
@@ -156,10 +156,10 @@
(define_insn_and_split "aarch64_atomic_exchange<mode>"
[(set (match_operand:ALLI 0 "register_operand" "=&r") ;; output
- (match_operand:ALLI 1 "aarch64_sync_memory_operand" "+Q")) ;; memory
+ (match_operand:ALLI 1 "aarch64_sync_memory_operand" "+Q")) ;; memory
(set (match_dup 1)
(unspec_volatile:ALLI
- [(match_operand:ALLI 2 "register_operand" "r") ;; input
+ [(match_operand:ALLI 2 "aarch64_reg_or_zero" "rZ") ;; input
(match_operand:SI 3 "const_int_operand" "")] ;; model
UNSPECV_ATOMIC_EXCHG))
(clobber (reg:CC CC_REGNUM))
@@ -175,22 +175,25 @@
}
)
-(define_insn_and_split "aarch64_atomic_exchange<mode>_lse"
- [(set (match_operand:ALLI 0 "register_operand" "=&r")
+(define_insn "aarch64_atomic_exchange<mode>_lse"
+ [(set (match_operand:ALLI 0 "register_operand" "=r")
(match_operand:ALLI 1 "aarch64_sync_memory_operand" "+Q"))
(set (match_dup 1)
(unspec_volatile:ALLI
- [(match_operand:ALLI 2 "register_operand" "r")
+ [(match_operand:ALLI 2 "aarch64_reg_or_zero" "rZ")
(match_operand:SI 3 "const_int_operand" "")]
UNSPECV_ATOMIC_EXCHG))]
"TARGET_LSE"
- "#"
- "&& reload_completed"
- [(const_int 0)]
{
- aarch64_gen_atomic_ldop (SET, operands[0], NULL, operands[1],
- operands[2], operands[3]);
- DONE;
+ enum memmodel model = memmodel_from_int (INTVAL (operands[3]));
+ if (is_mm_relaxed (model))
+ return "swp<atomic_sfx>\t%<w>2, %<w>0, %1";
+ else if (is_mm_acquire (model) || is_mm_consume (model))
+ return "swpa<atomic_sfx>\t%<w>2, %<w>0, %1";
+ else if (is_mm_release (model))
+ return "swpl<atomic_sfx>\t%<w>2, %<w>0, %1";
+ else
+ return "swpal<atomic_sfx>\t%<w>2, %<w>0, %1";
}
)
@@ -582,28 +585,6 @@
;; ARMv8.1-A LSE instructions.
-;; Atomic swap with memory.
-(define_insn "aarch64_atomic_swp<mode>"
- [(set (match_operand:ALLI 0 "register_operand" "+&r")
- (match_operand:ALLI 1 "aarch64_sync_memory_operand" "+Q"))
- (set (match_dup 1)
- (unspec_volatile:ALLI
- [(match_operand:ALLI 2 "register_operand" "r")
- (match_operand:SI 3 "const_int_operand" "")]
- UNSPECV_ATOMIC_SWP))]
- "TARGET_LSE && reload_completed"
- {
- enum memmodel model = memmodel_from_int (INTVAL (operands[3]));
- if (is_mm_relaxed (model))
- return "swp<atomic_sfx>\t%<w>2, %<w>0, %1";
- else if (is_mm_acquire (model) || is_mm_consume (model))
- return "swpa<atomic_sfx>\t%<w>2, %<w>0, %1";
- else if (is_mm_release (model))
- return "swpl<atomic_sfx>\t%<w>2, %<w>0, %1";
- else
- return "swpal<atomic_sfx>\t%<w>2, %<w>0, %1";
- })
-
;; Atomic load-op: Load data, operate, store result, keep data.
(define_insn "aarch64_atomic_load<atomic_ldop><mode>"
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