From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2153) id 4B3D2398B856; Thu, 17 Sep 2020 16:59:47 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 4B3D2398B856 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1600361987; bh=N0oYXVJ6g57LpmgF2jdgRT+jGfWI4vm72Z32KaCv3B8=; h=From:To:Subject:Date:From; b=DDQ27MgpIOriWvSJMufkU86McsKUCchpwup+MAMsT/Iv9UnujRiI/i6UyjItd/zjI sO6gyJJH6481RCqKV9272g/H0PI7KvjCxsBW7m9Yl8I+HZPkQ6Wb2UIr73BqULR9o9 iPO6iCZGcsJPV0y3SdR54qnwH+aj7Q45pNQ6Mip4= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Jakub Jelinek To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/vendors/redhat/heads/gcc-8-branch)] aarch64: Force TImode values into even registers X-Act-Checkin: gcc X-Git-Author: Andre Vieira X-Git-Refname: refs/vendors/redhat/heads/gcc-8-branch X-Git-Oldrev: a66cd821ebd80fe00092b7a7f4148b84949bd450 X-Git-Newrev: 3515256472b691b5b0b21496ee10029cc7b3cfb9 Message-Id: <20200917165947.4B3D2398B856@sourceware.org> Date: Thu, 17 Sep 2020 16:59:47 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Sep 2020 16:59:47 -0000 https://gcc.gnu.org/g:3515256472b691b5b0b21496ee10029cc7b3cfb9 commit 3515256472b691b5b0b21496ee10029cc7b3cfb9 Author: Andre Vieira Date: Wed Apr 29 15:42:27 2020 +0100 aarch64: Force TImode values into even registers The LSE CASP instruction requires values to be placed in even register pairs. A solution involving two additional register classes was rejected in favor of the much simpler solution of simply requiring all TImode values to be aligned. gcc/ChangeLog: 2020-04-29 Andre Vieira Backport from mainline. 2018-10-31 Richard Henderson * config/aarch64/aarch64.c (aarch64_hard_regno_mode_ok): Force 16-byte modes held in GP registers to use an even regno. Diff: --- gcc/ChangeLog | 8 ++++++++ gcc/config/aarch64/aarch64.c | 12 ++++++++---- 2 files changed, 16 insertions(+), 4 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index cc41f3685ad..d44ef73395a 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2020-04-29 Andre Vieira + + Backport from mainline. + 2018-10-31 Richard Henderson + + * config/aarch64/aarch64.c (aarch64_hard_regno_mode_ok): Force + 16-byte modes held in GP registers to use an even regno. + 2020-04-28 Andre Vieira PR target/94814 diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 5eec1aae54a..525deba56ea 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -1369,10 +1369,14 @@ aarch64_hard_regno_mode_ok (unsigned regno, machine_mode mode) if (regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM) return mode == Pmode; - if (GP_REGNUM_P (regno) && known_le (GET_MODE_SIZE (mode), 16)) - return true; - - if (FP_REGNUM_P (regno)) + if (GP_REGNUM_P (regno)) + { + if (known_le (GET_MODE_SIZE (mode), 8)) + return true; + else if (known_le (GET_MODE_SIZE (mode), 16)) + return (regno & 1) == 0; + } + else if (FP_REGNUM_P (regno)) { if (vec_flags & VEC_STRUCT) return end_hard_regno (mode, regno) - 1 <= V31_REGNUM;